plat/bcm/include/bcm963xx/6856_map_part.h

   1 /*
   2 <:copyright-BRCM:2015:DUAL/GPL:standard
   3
   4    Copyright (c) 2015 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22
  23 */
  24
  25 #ifndef __BCM6856_MAP_PART_H
  26 #define __BCM6856_MAP_PART_H
  27
  28 #ifdef __cplusplus
  29 extern "C" {
  30 #endif
  31
  32 #include "bcmtypes.h"
  33
  34 #define MEMC_PHYS_BASE          0x80180000
  35 #define MEMC_SIZE               0x24000
  36
  37 #define PMC_PHYS_BASE           0xffb00000
  38 #define PMC_SIZE                0x6000
  39 #define PROC_MON_PHYS_BASE      0xffb20000
  40 #define PROC_MON_SIZE           0x1000
  41 #define PMB_OFFSET              0x0100
  42
  43 #define PERF_PHYS_BASE          0xff800000
  44 #define PERF_SIZE               0x3000
  45 #define TIMR_OFFSET             0x0400
  46 #define WDTIMR0_OFFSET          0x0480
  47 #define WDTIMR1_OFFSET          0x04c0
  48
  49 #define BIUCFG_PHYS_BASE        0x81060000
  50 #define BIUCFG_SIZE             0x3000
  51 #define BIUCFG_OFFSET           0x0000
  52
  53 #define GIC_PHYS_BASE           0x81000000
  54 #define GIC_SIZE                0x10000
  55 #define GIC_OFFSET              0x0000
  56 #define GICD_OFFSET             0x1000
  57 #define GICC_OFFSET             0x2000
  58
  59
  60 #define PMC_BASE                (PMC_PHYS_BASE + 0)
  61 #define PROC_MON_BASE           (PROC_MON_PHYS_BASE + 0)
  62 #define PMB_BASE                (PROC_MON_PHYS_BASE + PMB_OFFSET)
  63
  64 #define WDTIMR0_BASE            (PERF_PHYS_BASE + WDTIMR0_OFFSET)
  65 #define TIMR_BASE               (PERF_PHYS_BASE + TIMR_OFFSET)
  66 #define BIUCFG_BASE             (BIUCFG_PHYS_BASE + BIUCFG_OFFSET)
  67
  68 #ifndef __ASSEMBLER__
  69 /*
  70  * Power Management Control
  71  */
  72 typedef struct PmcCtrlReg {
  73         uint32 gpTmr0Ctl;           /* 0x018 */
  74         uint32 gpTmr0Cnt;           /* 0x01c */
  75         uint32 gpTmr1Ctl;           /* 0x020 */
  76         uint32 gpTmr1Cnt;           /* 0x024 */
  77         uint32 hostMboxIn;          /* 0x028 */
  78         uint32 hostMboxOut;         /* 0x02c */
  79         uint32 reserved[4];         /* 0x030 */
  80         uint32 dmaCtrl;             /* 0x040 */
  81         uint32 dmaStatus;           /* 0x044 */
  82         uint32 dma0_3FifoStatus;    /* 0x048 */
  83         uint32 reserved1[4];        /* 0x04c */
  84         uint32 diagControl;         /* 0x05c */
  85         uint32 diagHigh;            /* 0x060 */
  86         uint32 diagLow;             /* 0x064 */
  87         uint32 reserved8;           /* 0x068 */
  88         uint32 addr1WndwMask;       /* 0x06c */
  89         uint32 addr1WndwBaseIn;     /* 0x070 */
  90         uint32 addr1WndwBaseOut;    /* 0x074 */
  91         uint32 addr2WndwMask;       /* 0x078 */
  92         uint32 addr2WndwBaseIn;     /* 0x07c */
  93         uint32 addr2WndwBaseOut;    /* 0x080 */
  94         uint32 scratch;             /* 0x084 */
  95         uint32 reserved9;           /* 0x088 */
  96         uint32 softResets;          /* 0x08c */
  97         uint32 reserved2;           /* 0x090 */
  98         uint32 m4keCoreStatus;      /* 0x094 */
  99         uint32 reserved3;           /* 0x098 */
 100         uint32 ubSlaveTimeout;      /* 0x09c */
 101         uint32 diagEn;              /* 0x0a0 */
 102         uint32 devTimeout;          /* 0x0a4 */
 103         uint32 ubusErrorOutMask;    /* 0x0a8 */
 104         uint32 diagCaptStopMask;    /* 0x0ac */
 105         uint32 revId;               /* 0x0b0 */
 106         uint32 gpTmr2Ctl;           /* 0x0b4 */
 107         uint32 gpTmr2Cnt;           /* 0x0b8 */
 108         uint32 reserved4[2];        /* 0x0bc */
 109         uint32 diagCtrl;            /* 0x0c4 */
 110         uint32 diagStat;            /* 0x0c8 */
 111         uint32 diagMask;            /* 0x0cc */
 112         uint32 diagRslt;            /* 0x0d0 */
 113         uint32 diagCmp;             /* 0x0d4 */
 114         uint32 diagCapt;            /* 0x0d8 */
 115         uint32 diagCnt;             /* 0x0dc */
 116         uint32 diagEdgeCnt;         /* 0x0e0 */
 117         uint32 reserved5[4];        /* 0x0e4 */
 118         uint32 smisc_bus_config;    /* 0x0f4 */
 119         uint32 lfsr;                /* 0x0f8 */
 120     uint32 dqm_pac_lock;        /* 0x0fc */
 121     uint32 l1_irq_4ke_mask;     /* 0x100 */
 122     uint32 l1_irq_4ke_status;   /* 0x104 */
 123     uint32 l1_irq_mips_mask;    /* 0x108 */
 124     uint32 l1_irq_mips_status;  /* 0x10c */
 125     uint32 l1_irq_mips1_mask;   /* 0x110 */
 126     uint32 reserved6[3];        /* 0x114 */
 127     uint32 l2_irq_gp_mask;      /* 0x120 */
 128     uint32 l2_irq_gp_status;    /* 0x124 */
 129     uint32 l2_irq_gp_set;       /* 0x128 */
 130     uint32 reserved7;           /* 0x12c */
 131     uint32 gp_in_irq_mask;      /* 0x130 */
 132     uint32 gp_in_irq_status;    /* 0x134 */
 133     uint32 gp_in_irq_set;       /* 0x138 */
 134     uint32 gp_in_irq_sense;     /* 0x13c */
 135     uint32 gp_in;               /* 0x140 */
 136     uint32 gp_out;              /* 0x144 */
 137 } PmcCtrlReg;
 138
 139 typedef struct PmcDmaReg {
 140         /* 0x00 */
 141         uint32 src;
 142         uint32 dest;
 143         uint32 cmdList;
 144         uint32 lenCtl;
 145         /* 0x10 */
 146         uint32 rsltSrc;
 147         uint32 rsltDest;
 148         uint32 rsltHcs;
 149         uint32 rsltLenStat;
 150 } PmcDmaReg;
 151
 152 typedef struct PmcTokenReg {
 153         /* 0x00 */
 154         uint32 bufSize;
 155         uint32 bufBase;
 156         uint32 idx2ptrIdx;
 157         uint32 idx2ptrPtr;
 158         /* 0x10 */
 159         uint32 unused[2];
 160         uint32 bufSize2;
 161 } PmcTokenReg;
 162
 163 typedef struct PmcPerfPowReg {
 164         uint32 freqScalarCtrl; /* 0x3c */
 165         uint32 freqScalarMask; /* 0x40 */
 166 } PmcPerfPowReg;
 167
 168 typedef struct PmcDQMPac {
 169     uint32 dqmPac[32];
 170 } PmcDQMPac;
 171
 172 typedef struct PmcDQMReg {
 173         uint32 cfg;                     /* 0x1c00 */
 174         uint32 _4keLowWtmkIrqMask;      /* 0x1c04 */
 175         uint32 mipsLowWtmkIrqMask;      /* 0x1c08 */
 176         uint32 lowWtmkIrqMask;          /* 0x1c0c */
 177         uint32 _4keNotEmptyIrqMask;     /* 0x1c10 */
 178         uint32 mipsNotEmptyIrqMask;     /* 0x1c14 */
 179         uint32 notEmptyIrqSts;          /* 0x1c18 */
 180         uint32 queueRst;                /* 0x1c1c */
 181         uint32 notEmptySts;             /* 0x1c20 */
 182         uint32 nextAvailMask;           /* 0x1c24 */
 183         uint32 nextAvailQueue;          /* 0x1c28 */
 184         uint32 mips1LowWtmkIrqMask;     /* 0x1c2c */
 185         uint32 mips1NotEmptyIrqMask;    /* 0x1c30 */
 186         uint32 autoSrcPidInsert;        /* 0x1c34 */
 187     uint32 timerIrqStatus;          /* 0x1c38 */
 188     uint32 timerStatus;             /* 0x1c3c */
 189     uint32 _4keTimerIrqMask;        /* 0x1c40 */
 190     uint32 mipsTimerIrqMask;        /* 0x1c44 */
 191     uint32 mips1TimerIrqMask;       /* 0x1c48 */
 192 } PmcDQMReg;
 193
 194 typedef struct PmcCntReg {
 195         uint32 cntr[10];
 196         uint32 unused[6];       /* 0x28-0x3f */
 197         uint32 cntrIrqMask;
 198         uint32 cntrIrqSts;
 199 } PmcCntReg;
 200
 201 typedef struct PmcDqmQCtrlReg {
 202         uint32 size;
 203         uint32 cfga;
 204         uint32 cfgb;
 205         uint32 cfgc;
 206 } PmcDqmQCtrlReg;
 207
 208 typedef struct PmcDqmQDataReg {
 209         uint32 word[4];
 210 } PmcDqmQDataReg;
 211
 212 typedef struct PmcDqmQMibReg {
 213         uint32 qNumFull[32];
 214         uint32 qNumEmpty[32];
 215         uint32 qNumPushed[32];
 216 } PmcDqmQMibReg;
 217
 218 typedef struct SSBMaster {
 219     uint32 ssbmControl;     /* 0x0060 */
 220     uint32 ssbmWrData;      /* 0x0064 */
 221     uint32 ssbmRdData;      /* 0x0068 */
 222     uint32 ssbmStatus;      /* 0x006c */
 223 } SSBMaster;
 224
 225 typedef struct PmmReg {
 226     uint32 memPowerCtrl;            /* 0x0000 */
 227     uint32 regSecurityConfig;       /* 0x0004 */
 228 } PmmReg;
 229
 230 typedef struct keyholeReg {
 231     uint32 ctrlSts;
 232     uint32 wrData;
 233     uint32 mutex;
 234     uint32 rdData;
 235 } keyholeReg;
 236
 237 typedef struct PmbBus {
 238     uint32 config;          /* 0x0100 */
 239     uint32 arbiter;         /* 0x0104 */
 240     uint32 timeout;         /* 0x0108 */
 241     uint32 unused1;         /* 0x010c */
 242     keyholeReg keyhole[4];  /* 0x0110-0x014f */
 243     uint32 unused2[44];     /* 0x0150-0x01ff */
 244     uint32 map[64];         /* 0x0200-0x02ff */
 245 }PmbBus;
 246
 247 typedef struct  CoreCtrl {
 248     uint32  coreEnable;         /* 0x0400 */
 249     uint32  autoresetControl;   /* 0x0404 */
 250     uint32  coreIdle;           /* 0x0408 */
 251     uint32  coreResetCause;     /* 0x040c */
 252     uint32  memPwrDownCtrl0;    /* 0x0410 */
 253     uint32  memPwrDownSts0;     /* 0x0414 */
 254     uint32  memPwrDownCtrl1;    /* 0x0418 */
 255     uint32  memPwrDownSts1;     /* 0x041c */
 256     uint32  sysFlg0Status;      /* 0x0420 */
 257     uint32  sysFlg0Set;         /* 0x0424 */
 258     uint32  sysFlg0Clear;       /* 0x0428 */
 259     uint32  unused1;            /* 0x042c */
 260     uint32  usrFlg0Status;      /* 0x0430 */
 261     uint32  usrFlg0Set;         /* 0x0434 */
 262     uint32  usrFlg0Clear;       /* 0x0438 */
 263     uint32  unused2;            /* 0x043c */
 264     uint32  subsystemRev;       /* 0x0440 */
 265     uint32  resetVector;        /* 0x0444 */
 266 } CoreCtrl;
 267
 268 typedef struct  CoreState {
 269     uint32  sysMbx[8];          /* 0x0480 */
 270     uint32  usrMbx[8];          /* 0x04a0 */
 271     uint32  sysMtx[4];          /* 0x04c0 */
 272     uint32  usrMtx[8];          /* 0x04d0 */
 273 } CoreState;
 274
 275 typedef struct  CoreIntr {
 276     uint32  irqStatus;          /* 0x0500 */
 277     uint32  irqSet;             /* 0x0504 */
 278     uint32  irqClear;           /* 0x0508 */
 279     uint32  unused1;            /* 0x050c */
 280     uint32  srqStatus;          /* 0x0510 */
 281     uint32  srqSet;             /* 0x0514 */
 282     uint32  srqClear;           /* 0x0518 */
 283     uint32  unused2;            /* 0x051c */
 284     uint32  drqStatus;          /* 0x0520 */
 285     uint32  drqSet;             /* 0x0524 */
 286     uint32  drqClear;           /* 0x0528 */
 287     uint32  unused3;            /* 0x052c */
 288     uint32  frqStatus;          /* 0x0530 */
 289     uint32  frqSet;             /* 0x0534 */
 290     uint32  frqClear;           /* 0x0538 */
 291     uint32  unused4;            /* 0x053c */
 292     uint32  hostIrqLatched;     /* 0x0540 */
 293     uint32  hostIrqSet;         /* 0x0544 */
 294     uint32  hostIrqClear;       /* 0x0548 */
 295     uint32  hostIrqEnable;      /* 0x054c */
 296     uint32  obusFaultStatus;    /* 0x0550 */
 297     uint32  obusFaultClear;     /* 0x0554 */
 298     uint32  obusFaultAddr;      /* 0x0558 */
 299 } CoreIntr;
 300
 301 typedef struct CoreProfile {
 302     uint32  mutex;              /* 0x0580 */
 303     uint32  lastConfPcLo;       /* 0x0584 */
 304     uint32  lastConfPcHi;       /* 0x0588 */
 305     uint32  lastPcLo;           /* 0x058c */
 306     uint32  lastPcHi;           /* 0x0590 */
 307     uint32  braTargetPc0Lo;     /* 0x0594 */
 308     uint32  braTargetPc0Hi;     /* 0x0598 */
 309     uint32  braTargetPc1Lo;     /* 0x059c */
 310     uint32  braTargetPc1Hi;     /* 0x05a0 */
 311     uint32  braTargetPc2Lo;     /* 0x05a4 */
 312     uint32  braTargetPc2Hi;     /* 0x05a8 */
 313     uint32  braTargetPc3Lo;     /* 0x05ac */
 314     uint32  braTargetPc3Hi;     /* 0x05b0 */
 315     uint32  unused[3];          /* 0x05b4-0x05bf */
 316     uint32  profSampleW[4];     /* 0x05c0 */
 317 } CoreProfile;
 318
 319 typedef struct MaestroMisc {
 320     CoreCtrl coreCtrl;          /* 0x0400 */
 321     uint32   unused1[14];       /* 0x0448-0x047f */
 322     CoreState coreState;        /* 0x0480 */
 323     uint32   unused2[4];        /* 0x04f0-0x04ff */
 324     CoreIntr interrupt;         /* 0x0500 */
 325     uint32   unused3[9];        /* 0x055c-0x057f */
 326     CoreProfile profile;        /* 0x0580 */
 327 } MaestroMisc;
 328
 329 typedef struct Pmc {
 330         uint32 baseReserved;                    /* 0x0000 */
 331         uint32 unused0[1029];
 332         PmcCtrlReg ctrl;                            /* 0x1018 */
 333
 334         uint32 unused1[174];                /* 0x1148-0x13ff */
 335
 336         PmcTokenReg token;                          /* 0x1400 */
 337         uint32 unused2[136];                    /* 0x141c-0x163b */
 338
 339         PmcPerfPowReg perfPower;                /* 0x163c */
 340         uint32 unused3[175];                    /* 0x1644-0x18ff */
 341
 342         PmcCntReg hwCounter;                    /* 0x1900 */
 343         uint32 unused4[110];                    /* 0x1948-0x1aff */
 344
 345     PmcDQMPac dqmPac;                   /* 0x1b00 */
 346     uint32 unused5[32];                 /* 0x1b80-0x1bff */
 347
 348         PmcDQMReg dqm;                              /* 0x1c00 */
 349         uint32 unused6[749];                    /* 0x1c4c-0x27ff */
 350
 351     uint32 qStatus[32];                     /* 0x2800 */
 352         uint32 unused7[480];                /* 0x2880-0x2fff */
 353
 354     PmcDqmQMibReg qMib;                     /* 0x3000 */
 355         uint32 unused8[928];                /* 0x3180-0x3fff */
 356
 357         PmcDqmQCtrlReg dqmQCtrl[8];         /* 0x4000 */
 358         uint32 unused9[992];                /* 0x4080-0x4fff */
 359
 360         PmcDqmQDataReg dqmQData[8];         /* 0x5000 */
 361 } Pmc;
 362 #define PMC ((volatile Pmc * const) PMC_BASE)
 363
 364 typedef struct Procmon {
 365     PmmReg  pmm;                        /* 0x20000 */
 366     uint32 unused11[22];                /* 0x20008-0x2005f */
 367
 368     SSBMaster ssbMasterCtrl;            /* 0x20060 */
 369     uint32 unused12[36];                /* 0x20070-0x200ff */
 370
 371     PmbBus pmb;                         /* 0x20100 */
 372     uint32 unused13[64];                /* 0x20300-0x203ff */
 373
 374     MaestroMisc maestroReg;             /* 0x20400 */
 375 } Procmon;
 376 #define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
 377
 378 typedef struct
 379 {
 380     uint32  control;
 381 #define PMC_PMBM_START                      (1 << 31)
 382 #define PMC_PMBM_TIMEOUT                    (1 << 30)
 383 #define PMC_PMBM_SLAVE_ERR                  (1 << 29)
 384 #define PMC_PMBM_BUSY                       (1 << 28)
 385 #define PMC_PMBM_BUS_SHIFT              (20)
 386 #define PMC_PMBM_Read                       (0 << 24)
 387 #define PMC_PMBM_Write                      (1 << 24)
 388     uint32  wr_data;
 389     uint32  mutex;
 390     uint32  rd_data;
 391 } PMB_keyhole_reg;
 392
 393 typedef struct PMBMaster {
 394     uint32 config;
 395 #define PMB_NUM_REGS_SHIFT (20)
 396 #define PMB_NUM_REGS_MASK  (0x3ff)
 397     uint32 arbitger;
 398     uint32 timeout;
 399     uint32 reserved;
 400     PMB_keyhole_reg keyhole[4];
 401     uint32 reserved1[44];
 402         uint32 map[64];
 403 } PMBMaster;
 404 #define PMB ((volatile PMBMaster * const) PMB_BASE)
 405
 406 /*
 407 ** Timer
 408 */
 409
 410 #define TIMER_64BIT
 411 typedef struct Timer {
 412     uint64        TimerCtl0;
 413     uint64        TimerCtl1;
 414     uint64        TimerCtl2;
 415     uint64        TimerCtl3;
 416 #define TIMERENABLE     (1ULL << 63)
 417 #define RSTCNTCLR       (1ULL << 62)
 418     uint64        TimerCnt0;
 419     uint64        TimerCnt1;
 420     uint64        TimerCnt2;
 421     uint64        TimerCnt3;
 422 #define TIMER_COUNT_MASK   0x3FFFFFFFFFFFFFFFULL
 423     uint32        TimerMask;
 424 #define TIMER0EN        0x01
 425 #define TIMER1EN        0x02
 426 #define TIMER2EN        0x04
 427 #define TIMER3EN        0x08
 428     uint32        TimerInts;
 429 #define TIMER0          0x01
 430 #define TIMER1          0x02
 431 #define TIMER2          0x04
 432 #define TIMER3          0x08
 433     uint32        ResetStatus;
 434 #define PCIE_RESET_STATUS       0x10000000
 435 #define SW_RESET_STATUS         0x20000000
 436 #define HW_RESET_STATUS         0x40000000
 437 #define POR_RESET_STATUS        0x80000000
 438 #define RESET_STATUS_MASK       0xF0000000
 439     uint32        ResetReason;
 440 #define SW_INI_RESET            0x00000001
 441     uint32        spare[3];
 442 } Timer;
 443
 444 typedef struct WDTimer {
 445     uint32        WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer
 446      * Write 0xee00 0x00ee to Stop and re-load default count
 447      *      * Read from this register returns current watch dog count
 448      *           */
 449     uint32        WatchDogCtl;
 450
 451     /* Number of 50-MHz ticks for WD Reset pulse to last */
 452     uint32        WDResetCount;
 453
 454     uint32        SoftRst;
 455 #define SOFT_RESET              0x00000001
 456     uint32        WDAccessCtl;
 457 } WDTimer;
 458
 459 #define TIMER    ((volatile Timer * const) TIMR_BASE)
 460 #define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE)
 461
 462 typedef struct BIUCFG_Access {
 463     uint32 permission;        /* 0x0 */
 464     uint32 sbox;              /* 0x4 */
 465     uint32 cpu_defeature;     /* 0x8 */
 466     uint32 dbg_security;      /* 0xc */
 467     uint32 rsvd1[32];         /* 0x10 - 0x8f */
 468     uint64 violation[2];      /* 0x90 - 0x9f */
 469     uint32 ts_access[2];      /* 0xa0 - 0xa7 */
 470     uint32 rsvd2[22];         /* 0xa8 - 0xff */
 471 }BIUCFG_Access;
 472
 473 typedef struct BIUCFG_Cluster {
 474     uint32 permission;        /* 0x0 */
 475     uint32 config;            /* 0x4 */
 476     uint32 status;            /* 0x8 */
 477     uint32 control;           /* 0xc */
 478     uint32 cpucfg;            /* 0x10 */
 479     uint32 dbgrom;            /* 0x14 */
 480     uint32 rsvd1[2];          /* 0x18 - 0x1f */
 481     uint64 rvbar_addr[4];     /* 0x20 - 0x3f */
 482     uint32 rsvd2[48];         /* 0x40 - 0xff */
 483 }BIUCFG_Cluster;
 484
 485 typedef struct BIUCFG_AuxClkCtrl {
 486     uint32 clk_control;       /* 0x0 */
 487     uint32 clk_ramp;          /* 0x4 */
 488     uint32 clk_pattern;       /* 0x8 */
 489     uint32 rsvd;              /* 0xC */
 490 } BIUCFG_AuxClkCtrl;
 491
 492 typedef struct BIUCFG_Aux {
 493     uint32            permission;         /* 0 */
 494     uint32            rsvd1[3];           /* 0x04 - 0x0c */
 495     BIUCFG_AuxClkCtrl cluster_clkctrl[2]; /* 0x10 - 0x2c */
 496     uint32            rsvd2[52];          /* 0x30 - 0xFF */
 497 } BIUCFG_Aux;
 498
 499
 500 typedef struct BIUCFG {
 501     BIUCFG_Access  access;        /* 0x0 - 0xff*/
 502     BIUCFG_Cluster cluster[1];    /* 0x100 - 0x1ff*/
 503     uint32         rsvd1[320];    /* 0x200 - 0x6ff */
 504     BIUCFG_Aux     aux;           /* 0x700 - 0x7ff */
 505     uint32         rsvd2[2560];   /* 0x800 - 0x2fff */
 506
 507 }BIUCFG;
 508
 509 #define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
 510
 511 #endif /* __ASSEMBLER__ */
 512
 513 #ifdef __cplusplus
 514 }
 515 #endif
 516
 517 #endif