2 <:copyright-BRCM:2015:DUAL/GPL:standard
4 Copyright (c) 2015 Broadcom
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License, version 2, as published by
9 the Free Software Foundation (the "GPL").
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA.
25 #ifndef __BCM6858_MAP_PART_H
26 #define __BCM6858_MAP_PART_H
34 #define MEMC_PHYS_BASE 0x80180000
35 #define MEMC_SIZE 0x24000
37 #define PMC_PHYS_BASE 0x80200000
38 #define PMC_SIZE 0x5000
39 #define PROC_MON_PHYS_BASE 0x80280000
40 #define PROC_MON_SIZE 0x1000
42 #define PERF_PHYS_BASE 0xff800000
43 #define PERF_SIZE 0x3000
44 #define TIMR_OFFSET 0x2700
45 #define WDTIMR0_OFFSET 0x2780
46 #define WDTIMR1_OFFSET 0x27c0
48 #define BIUCFG_PHYS_BASE 0x81060000
49 #define BIUCFG_SIZE 0x3000
50 #define BIUCFG_OFFSET 0x0000
52 #define GIC_PHYS_BASE 0x81000000
53 #define GIC_SIZE 0x10000
54 #define GIC_OFFSET 0x0000
55 #define GICD_OFFSET 0x1000
56 #define GICC_OFFSET 0x2000
58 #define PMC_BASE (PMC_PHYS_BASE + 0)
59 #define PROC_MON_BASE (PROC_MON_PHYS_BASE + 0)
61 #define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET)
62 #define TIMR_BASE (PERF_PHYS_BASE + TIMR_OFFSET)
64 #define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET)
68 * Power Management Control
70 typedef struct PmcCtrlReg
{
73 uint32 l1Irq4keStatus
;
75 uint32 l1IrqMipsStatus
;
87 #define PMC_CTRL_GP_FLASH_BOOT_STALL 0x00000080
95 uint32 dma0_3FifoStatus
;
96 uint32 unused0
[3]; /* 0x4c-0x57 */
98 uint32 l1IrqMips1Mask
;
104 uint32 addr1WndwMask
;
106 uint32 addr1WndwBaseIn
;
107 uint32 addr1WndwBaseOut
;
108 uint32 addr2WndwMask
;
109 uint32 addr2WndwBaseIn
;
111 uint32 addr2WndwBaseOut
;
116 uint32 eb2ubusTimeout
;
117 uint32 m4keCoreStatus
;
119 uint32 ubSlaveTimeout
;
123 uint32 ubusErrorOutMask
;
124 uint32 diagCaptStopMask
;
142 uint32 unused1
[4]; /* 0xe4-0xf3 */
144 uint32 iopPeriphBaseAddr
;
146 uint32 unused2
; /* 0xfc-0xff */
149 typedef struct PmcOutFifoReg
{
150 uint32 msgCtrl
; /* 0x00 */
151 uint32 msgSts
; /* 0x04 */
152 uint32 unused
[14]; /* 0x08-0x3f */
153 uint32 msgData
[16]; /* 0x40-0x7c */
156 typedef struct PmcInFifoReg
{
157 uint32 msgCtrl
; /* 0x00 */
158 uint32 msgSts
; /* 0x04 */
159 uint32 unused
[13]; /* 0x08-0x3b */
160 uint32 msgLast
; /* 0x3c */
161 uint32 msgData
[16]; /* 0x40-0x7c */
164 typedef struct PmcDmaReg
{
177 typedef struct PmcTokenReg
{
188 typedef struct PmcPerfPowReg
{
195 uint32 instnComplete
;
208 uint32 freqScalarCtrl
;
210 uint32 freqScalarMask
;
213 typedef struct PmcDQMReg
{
216 uint32 _4keLowWtmkIrqMask
;
217 uint32 mipsLowWtmkIrqMask
;
218 uint32 lowWtmkIrqMask
;
220 uint32 _4keNotEmptyIrqMask
;
221 uint32 mipsNotEmptyIrqMask
;
222 uint32 notEmptyIrqSts
;
226 uint32 nextAvailMask
;
227 uint32 nextAvailQueue
;
228 uint32 mips1LowWtmkIrqMask
;
230 uint32 mips1NotEmptyIrqMask
;
231 uint32 autoSrcPidInsert
;
234 typedef struct PmcCntReg
{
236 uint32 unused
[6]; /* 0x28-0x3f */
241 typedef struct PmcDqmQCtrlReg
{
248 typedef struct PmcDqmQDataReg
{
252 typedef struct PmcDqmQMibReg
{
254 uint32 qNumEmpty
[32];
255 uint32 qNumPushed
[32];
259 uint32 baseReserved
; /* 0x0000 */
260 uint32 unused0
[1023];
261 PmcCtrlReg ctrl
; /* 0x1000 */
263 PmcOutFifoReg outFifo
; /* 0x1100 */
264 uint32 unused1
[32]; /* 0x1180-0x11ff */
265 PmcInFifoReg inFifo
; /* 0x1200 */
266 uint32 unused2
[32]; /* 0x1280-0x12ff */
268 PmcDmaReg dma
[2]; /* 0x1300 */
269 uint32 unused3
[48]; /* 0x1340-0x13ff */
271 PmcTokenReg token
; /* 0x1400 */
272 uint32 unused4
[121]; /* 0x141c-0x15ff */
274 PmcPerfPowReg perfPower
; /* 0x1600 */
275 uint32 unused5
[47]; /* 0x1644-0x16ff */
277 uint32 msgId
[32]; /* 0x1700 */
278 uint32 unused6
[32]; /* 0x1780-0x17ff */
280 PmcDQMReg dqm
; /* 0x1800 */
281 uint32 unused7
[50]; /* 0x1838-0x18ff */
283 PmcCntReg hwCounter
; /* 0x1900 */
284 uint32 unused8
[46]; /* 0x1948-0x19ff */
286 PmcDqmQCtrlReg dqmQCtrl
[32]; /* 0x1a00 */
287 PmcDqmQDataReg dqmQData
[32]; /* 0x1c00 */
288 uint32 unused9
[64]; /* 0x1e00-0x1eff */
290 uint32 qStatus
[32]; /* 0x1f00 */
291 uint32 unused10
[32]; /* 0x1f80-0x1fff */
293 PmcDqmQMibReg qMib
; /* 0x2000 */
294 uint32 unused11
[1952]; /* 0x2180-0x3ffff */
296 uint32 sharedMem
[8192]; /* 0x4000-0xbffc */
299 #define PMC ((volatile Pmc * const) PMC_BASE)
302 * Process Monitor Module
304 typedef struct PMRingOscillatorControl
{
312 } PMRingOscillatorControl
;
314 #define RCAL_0P25UM_HORZ 0
315 #define RCAL_0P25UM_VERT 1
316 #define RCAL_0P5UM_HORZ 2
317 #define RCAL_0P5UM_VERT 3
318 #define RCAL_1UM_HORZ 4
319 #define RCAL_1UM_VERT 5
320 #define PMMISC_RMON_EXT_REG ((RCAL_1UM_VERT + 1)/2)
321 #define PMMISC_RMON_VALID_MASK (0x1<<16)
322 typedef struct PMMiscControl
{
329 typedef struct PMSSBMasterControl
{
333 } PMSSBMasterControl
;
335 typedef struct PMEctrControl
{
343 typedef struct PMBMaster
{
345 #define PMC_PMBM_START (1 << 31)
346 #define PMC_PMBM_TIMEOUT (1 << 30)
347 #define PMC_PMBM_SLAVE_ERR (1 << 29)
348 #define PMC_PMBM_BUSY (1 << 28)
349 #define PMC_PMBM_Read (0 << 20)
350 #define PMC_PMBM_Write (1 << 20)
357 typedef struct PMAPVTMONControl
{
374 typedef struct PMUBUSCfg
{
379 typedef struct ProcessMonitorRegs
{
380 uint32 MonitorCtrl
; /* 0x00 */
382 PMRingOscillatorControl ROSC
; /* 0x20 */
384 PMMiscControl Misc
; /* 0x40 */
385 PMSSBMasterControl SSBMaster
; /* 0x60 */
387 PMEctrControl Ectr
; /* 0x80 */
389 PMBMaster PMBM
[2]; /* 0xc0 */
390 PMAPVTMONControl APvtmonCtrl
; /* 0x100 */
392 PMUBUSCfg UBUSCfg
; /* 0x160 */
393 } ProcessMonitorRegs
;
395 #define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE)
402 typedef struct Timer
{
407 #define TIMERENABLE (1ULL << 63)
408 #define RSTCNTCLR (1ULL << 62)
413 #define TIMER_COUNT_MASK 0x3FFFFFFFFFFFFFFFULL
415 #define TIMER0EN 0x01
416 #define TIMER1EN 0x02
417 #define TIMER2EN 0x04
418 #define TIMER3EN 0x08
425 #define PCIE_RESET_STATUS 0x10000000
426 #define SW_RESET_STATUS 0x20000000
427 #define HW_RESET_STATUS 0x40000000
428 #define POR_RESET_STATUS 0x80000000
429 #define RESET_STATUS_MASK 0xF0000000
431 #define SW_INI_RESET 0x00000001
435 typedef struct WDTimer
{
436 uint32 WatchDogDefCount
;/* Write 0xff00 0x00ff to Start timer
437 * Write 0xee00 0x00ee to Stop and re-load default count
438 * * Read from this register returns current watch dog count
442 /* Number of 50-MHz ticks for WD Reset pulse to last */
446 #define SOFT_RESET 0x00000001
450 #define TIMER ((volatile Timer * const) TIMR_BASE)
451 #define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE)
453 typedef struct BIUCFG_Access
{
454 uint32 permission
; /* 0x0 */
455 uint32 sbox
; /* 0x4 */
456 uint32 cpu_defeature
; /* 0x8 */
457 uint32 dbg_security
; /* 0xc */
458 uint32 rsvd1
[32]; /* 0x10 - 0x8f */
459 uint64 violation
[2]; /* 0x90 - 0x9f */
460 uint32 ts_access
[2]; /* 0xa0 - 0xa7 */
461 uint32 rsvd2
[22]; /* 0xa8 - 0xff */
464 typedef struct BIUCFG_Cluster
{
465 uint32 permission
; /* 0x0 */
466 uint32 config
; /* 0x4 */
467 uint32 status
; /* 0x8 */
468 uint32 control
; /* 0xc */
469 uint32 cpucfg
; /* 0x10 */
470 uint32 dbgrom
; /* 0x14 */
471 uint32 rsvd1
[2]; /* 0x18 - 0x1f */
472 uint32 rvbar_addr
[4]; /* 0x20 - 0x2f */
473 uint32 rsvd2
[52]; /* 0x30 - 0xff */
476 typedef struct BIUCFG_AuxClkCtrl
{
477 uint32 clk_control
; /* 0x0 */
478 uint32 clk_ramp
; /* 0x4 */
479 uint32 clk_pattern
; /* 0x8 */
480 uint32 rsvd
; /* 0xC */
483 typedef struct BIUCFG_Aux
{
484 uint32 permission
; /* 0 */
485 uint32 rsvd1
[3]; /* 0x04 - 0x0c */
486 BIUCFG_AuxClkCtrl cluster_clkctrl
[2]; /* 0x10 - 0x2c */
487 uint32 rsvd2
[52]; /* 0x30 - 0xFF */
490 typedef struct BIUCFG
{
491 BIUCFG_Access access
; /* 0x0 - 0xff*/
492 BIUCFG_Cluster cluster
[1]; /* 0x100 - 0x1ff*/
493 uint32 rsvd1
[320]; /* 0x200 - 0x6ff */
494 BIUCFG_Aux aux
; /* 0x700 - 0x7ff */
495 uint32 rsvd2
[2560]; /* 0x800 - 0x2fff */
498 #define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
500 #endif /* __ASSEMBLER__ */