2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
7 #include <arch_helpers.h>
11 #include <delay_timer.h>
12 #include <desc_image_load.h>
17 #include <hisi_sram_map.h>
21 #include <optee_utils.h>
25 #include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
28 #include "hikey_private.h"
31 * The next 2 constants identify the extents of the code & RO data region.
32 * These addresses are used by the MMU setup code and therefore they must be
33 * page-aligned. It is the responsibility of the linker script to ensure that
34 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
36 #define BL2_RO_BASE (unsigned long)(&__RO_START__)
37 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
39 #define BL2_RW_BASE (BL2_RO_LIMIT)
42 * The next 2 constants identify the extents of the coherent memory region.
43 * These addresses are used by the MMU setup code and therefore they must be
44 * page-aligned. It is the responsibility of the linker script to ensure that
45 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
46 * page-aligned addresses.
48 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
49 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
51 static meminfo_t bl2_el3_tzram_layout
;
52 static console_pl011_t console
;
55 BOOT_MODE_RECOVERY
= 0,
60 /*******************************************************************************
61 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
62 * Return 0 on success, -1 otherwise.
63 ******************************************************************************/
64 int plat_hikey_bl2_handle_scp_bl2(image_info_t
*scp_bl2_image_info
)
67 hisi_mcu_enable_sram();
69 /* Load MCU binary into SRAM */
70 hisi_mcu_load_image(scp_bl2_image_info
->image_base
,
71 scp_bl2_image_info
->image_size
);
75 INFO("%s: MCU PC is at 0x%x\n",
76 __func__
, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2
));
77 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n",
78 __func__
, mmio_read_32(AO_SC_PERIPH_CLKSTAT4
));
82 /*******************************************************************************
83 * Gets SPSR for BL32 entry
84 ******************************************************************************/
85 uint32_t hikey_get_spsr_for_bl32_entry(void)
88 * The Secure Payload Dispatcher service is responsible for
89 * setting the SPSR prior to entry into the BL3-2 image.
94 /*******************************************************************************
95 * Gets SPSR for BL33 entry
96 ******************************************************************************/
98 uint32_t hikey_get_spsr_for_bl33_entry(void)
103 /* Figure out what mode we enter the non-secure world in */
104 mode
= (el_implemented(2) != EL_IMPL_NONE
) ? MODE_EL2
: MODE_EL1
;
107 * TODO: Consider the possibility of specifying the SPSR in
108 * the FIP ToC and allowing the platform to have a say as
111 spsr
= SPSR_64(mode
, MODE_SP_ELX
, DISABLE_ALL_EXCEPTIONS
);
115 uint32_t hikey_get_spsr_for_bl33_entry(void)
117 unsigned int hyp_status
, mode
, spsr
;
119 hyp_status
= GET_VIRT_EXT(read_id_pfr1());
121 mode
= (hyp_status
) ? MODE32_hyp
: MODE32_svc
;
124 * TODO: Consider the possibility of specifying the SPSR in
125 * the FIP ToC and allowing the platform to have a say as
128 spsr
= SPSR_MODE32(mode
, plat_get_ns_image_entrypoint() & 0x1,
129 SPSR_E_LITTLE
, DISABLE_ALL_EXCEPTIONS
);
134 int hikey_bl2_handle_post_image_load(unsigned int image_id
)
137 bl_mem_params_node_t
*bl_mem_params
= get_bl_mem_params_node(image_id
);
139 bl_mem_params_node_t
*pager_mem_params
= NULL
;
140 bl_mem_params_node_t
*paged_mem_params
= NULL
;
142 assert(bl_mem_params
);
148 pager_mem_params
= get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID
);
149 assert(pager_mem_params
);
151 paged_mem_params
= get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID
);
152 assert(paged_mem_params
);
154 err
= parse_optee_header(&bl_mem_params
->ep_info
,
155 &pager_mem_params
->image_info
,
156 &paged_mem_params
->image_info
);
158 WARN("OPTEE header parse error.\n");
161 bl_mem_params
->ep_info
.spsr
= hikey_get_spsr_for_bl32_entry();
166 /* BL33 expects to receive the primary CPU MPID (through r0) */
167 bl_mem_params
->ep_info
.args
.arg0
= 0xffff & read_mpidr();
168 bl_mem_params
->ep_info
.spsr
= hikey_get_spsr_for_bl33_entry();
172 case SCP_BL2_IMAGE_ID
:
173 /* The subsequent handling of SCP_BL2 is platform specific */
174 err
= plat_hikey_bl2_handle_scp_bl2(&bl_mem_params
->image_info
);
176 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
181 /* Do nothing in default case */
188 /*******************************************************************************
189 * This function can be used by the platforms to update/use image
190 * information for given `image_id`.
191 ******************************************************************************/
192 int bl2_plat_handle_post_image_load(unsigned int image_id
)
194 return hikey_bl2_handle_post_image_load(image_id
);
197 static void reset_dwmmc_clk(void)
201 /* disable mmc0 bus clock */
202 mmio_write_32(PERI_SC_PERIPH_CLKDIS0
, PERI_CLK0_MMC0
);
204 data
= mmio_read_32(PERI_SC_PERIPH_CLKSTAT0
);
205 } while (data
& PERI_CLK0_MMC0
);
206 /* enable mmc0 bus clock */
207 mmio_write_32(PERI_SC_PERIPH_CLKEN0
, PERI_CLK0_MMC0
);
209 data
= mmio_read_32(PERI_SC_PERIPH_CLKSTAT0
);
210 } while (!(data
& PERI_CLK0_MMC0
));
211 /* reset mmc0 clock domain */
212 mmio_write_32(PERI_SC_PERIPH_RSTEN0
, PERI_RST0_MMC0
);
214 /* bypass mmc0 clock phase */
215 data
= mmio_read_32(PERI_SC_PERIPH_CTRL2
);
217 mmio_write_32(PERI_SC_PERIPH_CTRL2
, data
);
219 /* disable low power */
220 data
= mmio_read_32(PERI_SC_PERIPH_CTRL13
);
222 mmio_write_32(PERI_SC_PERIPH_CTRL13
, data
);
224 data
= mmio_read_32(PERI_SC_PERIPH_RSTSTAT0
);
225 } while (!(data
& PERI_RST0_MMC0
));
227 /* unreset mmc0 clock domain */
228 mmio_write_32(PERI_SC_PERIPH_RSTDIS0
, PERI_RST0_MMC0
);
230 data
= mmio_read_32(PERI_SC_PERIPH_RSTSTAT0
);
231 } while (data
& PERI_RST0_MMC0
);
234 static void hikey_boardid_init(void)
239 mmio_write_32(MEMORY_AXI_CHIP_ADDR
, midr
);
240 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR
,
243 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR
, 0);
244 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR
, 0x2b);
246 mmio_write_32(ACPU_ARM64_FLAGA
, 0x1234);
247 mmio_write_32(ACPU_ARM64_FLAGB
, 0x5678);
250 static void hikey_sd_init(void)
252 /* switch pinmux to SD */
253 mmio_write_32(IOMG_SD_CLK
, IOMG_MUX_FUNC0
);
254 mmio_write_32(IOMG_SD_CMD
, IOMG_MUX_FUNC0
);
255 mmio_write_32(IOMG_SD_DATA0
, IOMG_MUX_FUNC0
);
256 mmio_write_32(IOMG_SD_DATA1
, IOMG_MUX_FUNC0
);
257 mmio_write_32(IOMG_SD_DATA2
, IOMG_MUX_FUNC0
);
258 mmio_write_32(IOMG_SD_DATA3
, IOMG_MUX_FUNC0
);
260 mmio_write_32(IOCG_SD_CLK
, IOCG_INPUT_16MA
);
261 mmio_write_32(IOCG_SD_CMD
, IOCG_INPUT_12MA
);
262 mmio_write_32(IOCG_SD_DATA0
, IOCG_INPUT_12MA
);
263 mmio_write_32(IOCG_SD_DATA1
, IOCG_INPUT_12MA
);
264 mmio_write_32(IOCG_SD_DATA2
, IOCG_INPUT_12MA
);
265 mmio_write_32(IOCG_SD_DATA3
, IOCG_INPUT_12MA
);
267 /* set SD Card detect as nopull */
268 mmio_write_32(IOCG_GPIO8
, 0);
271 static void hikey_jumper_init(void)
273 /* set jumper detect as nopull */
274 mmio_write_32(IOCG_GPIO24
, 0);
275 /* set jumper detect as GPIO */
276 mmio_write_32(IOMG_GPIO24
, IOMG_MUX_FUNC0
);
279 void bl2_el3_early_platform_setup(u_register_t arg1
, u_register_t arg2
,
280 u_register_t arg3
, u_register_t arg4
)
282 /* Initialize the console to provide early debug support */
283 console_pl011_register(CONSOLE_BASE
, PL011_UART_CLK_IN_HZ
,
284 PL011_BAUDRATE
, &console
);
286 * Allow BL2 to see the whole Trusted RAM.
288 bl2_el3_tzram_layout
.total_base
= BL2_RW_BASE
;
289 bl2_el3_tzram_layout
.total_size
= BL31_LIMIT
- BL2_RW_BASE
;
292 void bl2_el3_plat_arch_setup(void)
294 hikey_init_mmu_el3(bl2_el3_tzram_layout
.total_base
,
295 bl2_el3_tzram_layout
.total_size
,
298 BL2_COHERENT_RAM_BASE
,
299 BL2_COHERENT_RAM_LIMIT
);
302 void bl2_platform_setup(void)
304 dw_mmc_params_t params
;
305 struct mmc_device_info info
;
311 /* Clear SRAM since it'll be used by MCU right now. */
312 memset((void *)SRAM_BASE
, 0, SRAM_SIZE
);
315 hikey_ddr_init(DDR_FREQ_800M
);
316 hikey_security_setup();
318 hikey_boardid_init();
324 hikey_mmc_pll_init();
326 /* Clean SRAM before MCU used */
327 clean_dcache_range(SRAM_BASE
, SRAM_SIZE
);
330 memset(¶ms
, 0, sizeof(dw_mmc_params_t
));
331 params
.reg_base
= DWMMC0_BASE
;
332 params
.desc_base
= HIKEY_MMC_DESC_BASE
;
333 params
.desc_size
= 1 << 20;
334 params
.clk_rate
= 24 * 1000 * 1000;
335 params
.bus_width
= MMC_BUS_WIDTH_8
;
336 params
.flags
= MMC_FLAG_CMD23
;
337 info
.mmc_dev_type
= MMC_IS_EMMC
;
338 dw_mmc_init(¶ms
, &info
);