2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
10 #include <drivers/arm/cci.h>
11 #include <drivers/arm/gicv2.h>
13 #include <platform_def.h>
15 .section .rodata.gic_reg_name, "aS"
17 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
19 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
25 .section .rodata.cci_reg_name, "aS"
27 .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
29 /* ---------------------------------------------
30 * The below macro prints out relevant GIC
31 * registers whenever an unhandled exception is
33 * ---------------------------------------------
35 .macro plat_crash_print_regs
36 mov_imm x16, GICD_REG_BASE
37 mov_imm x17, GICC_REG_BASE
39 /* Load the gicc reg list to x6 */
41 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
42 ldr w8, [x17, #GICC_HPPIR]
43 ldr w9, [x17, #GICC_AHPPIR]
44 ldr w10, [x17, #GICC_CTLR]
45 /* Store to the crash buf and print to cosole */
46 bl str_in_crash_buf_print
48 /* Print the GICD_ISPENDR regs */
49 add x7, x16, #GICD_ISPENDR
65 adr x6, cci_iface_regs
66 /* Store in x7 the base address of the first interface */
67 mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
68 CCI400_SL_IFACE3_CLUSTER_IX))
69 ldr w8, [x7, #SNOOP_CTRL_REG]
70 /* Store in x7 the base address of the second interface */
71 mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
72 CCI400_SL_IFACE4_CLUSTER_IX))
73 ldr w9, [x7, #SNOOP_CTRL_REG]
74 /* Store to the crash buf and print to console */
75 bl str_in_crash_buf_print
78 #endif /* PLAT_MACROS_S */