0aed1e142f80f0cba88c17461faa3a5f1ef56bc0
[project/bcm63xx/atf.git] / plat / imx / common / include / imx_snvs.h
1 /*
2 * Copyright (C) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #ifndef IMX_SNVS_H
7 #define IMX_SNVS_H
8
9 #include <stdint.h>
10 #include <arch.h>
11
12 struct snvs {
13 uint32_t hplr;
14 uint32_t hpcomr;
15 uint32_t hpcr;
16 uint32_t hpsicr;
17 uint32_t hpsvcr;
18 uint32_t hpsr;
19 uint32_t hpsvsr;
20 uint32_t hphacivr;
21 uint32_t hphacr;
22 uint32_t hprtcmr;
23 uint32_t hprtclr;
24 uint32_t hptamr;
25 uint32_t hptalr;
26 uint32_t lplr;
27 uint32_t lpcr;
28 uint32_t lpmkcr;
29 uint32_t lpsvcr;
30 uint32_t lptgfcr;
31 uint32_t lptdcr;
32 uint32_t lpsr;
33 uint32_t lpsrtcmr;
34 uint32_t lpsrtclr;
35 uint32_t lptar;
36 uint32_t lpsmcmr;
37 uint32_t lpsmclr;
38 uint32_t lppgdr;
39 uint32_t lpgpr0_alias;
40 uint8_t lpzmkr[32];
41 uint16_t res0;
42 uint32_t lpgpr0[4];
43 uint32_t lptdc2r;
44 uint32_t lptdsr;
45 uint32_t lptgf1cr;
46 uint32_t lptgf2cr;
47 uint32_t res1[4];
48 uint32_t lpat1cr;
49 uint32_t lpat2cr;
50 uint32_t lpat3cr;
51 uint32_t lpat4cr;
52 uint32_t lpat5cr;
53 uint32_t res2[3];
54 uint32_t lpatctlr;
55 uint32_t lpatclkr;
56 uint32_t lpatrc1r;
57 uint32_t lpatrc2r;
58 uint32_t res3[706];
59 uint32_t hpvidr1;
60 uint32_t hpvidr2;
61 } __packed;
62
63 /* Define the HPCOMR bits */
64 #define HPCOMR_NPSWA_EN BIT(31)
65 #define HPCOMR_HAC_STOP BIT(19)
66 #define HPCOMR_HAC_CLEAR BIT(18)
67 #define HPCOMR_HAC_LOAD BIT(17)
68 #define HPCOMR_HAC_EN BIT(16)
69 #define HPCOMR_MKS_EN BIT(13)
70 #define HPCOMR_PROG_ZMK BIT(12)
71 #define HPCOMR_SW_LPSV BIT(10)
72 #define HPCOMR_SW_FSV BIT(9)
73 #define HPCOMR_SW_SV BIT(8)
74 #define HPCOMR_LP_SWR_DIS BIT(5)
75 #define HPCOMR_LP_SWR BIT(4)
76 #define HPCOMR_SSM_SFNS_DIS BIT(2)
77 #define HPCOMR_SSM_ST_DIS BIT(1)
78 #define HPCOMR_SSM_ST BIT(0)
79
80 void imx_snvs_init(void);
81
82 #endif /* IMX_SNVS_H */