plat/imx/common/plat_imx8_gic.c

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <platform_def.h>
   8
   9 #include <common/bl_common.h>
  10 #include <common/interrupt_props.h>
  11 #include <drivers/arm/gicv3.h>
  12 #include <lib/utils.h>
  13 #include <plat/common/platform.h>
  14
  15 #include <plat_imx8.h>
  16
  17 /* the GICv3 driver only needs to be initialized in EL3 */
  18 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
  19
  20 static const interrupt_prop_t g01s_interrupt_props[] = {
  21         INTR_PROP_DESC(6, GIC_HIGHEST_SEC_PRIORITY,
  22                        INTR_GROUP1S, GIC_INTR_CFG_LEVEL),
  23         INTR_PROP_DESC(7, GIC_HIGHEST_SEC_PRIORITY,
  24                        INTR_GROUP0, GIC_INTR_CFG_LEVEL),
  25 };
  26
  27 static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr)
  28 {
  29         return (unsigned int)plat_core_pos_by_mpidr(mpidr);
  30 }
  31
  32 const gicv3_driver_data_t arm_gic_data = {
  33         .gicd_base = PLAT_GICD_BASE,
  34         .gicr_base = PLAT_GICR_BASE,
  35         .interrupt_props = g01s_interrupt_props,
  36         .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
  37         .rdistif_num = PLATFORM_CORE_COUNT,
  38         .rdistif_base_addrs = rdistif_base_addrs,
  39         .mpidr_to_core_pos = plat_imx_mpidr_to_core_pos,
  40 };
  41
  42 void plat_gic_driver_init(void)
  43 {
  44         /*
  45          * the GICv3 driver is initialized in EL3 and does not need
  46          * to be initialized again in S-EL1. This is because the S-EL1
  47          * can use GIC system registers to manage interrupts and does
  48          * not need GIC interface base addresses to be configured.
  49          */
  50 #if IMAGE_BL31
  51         gicv3_driver_init(&arm_gic_data);
  52 #endif
  53 }
  54
  55 void plat_gic_init(void)
  56 {
  57         gicv3_distif_init();
  58         gicv3_rdistif_init(plat_my_core_pos());
  59         gicv3_cpuif_enable(plat_my_core_pos());
  60 }
  61
  62 void plat_gic_cpuif_enable(void)
  63 {
  64         gicv3_cpuif_enable(plat_my_core_pos());
  65 }
  66
  67 void plat_gic_cpuif_disable(void)
  68 {
  69         gicv3_cpuif_disable(plat_my_core_pos());
  70 }
  71
  72 void plat_gic_pcpu_init(void)
  73 {
  74         gicv3_rdistif_init(plat_my_core_pos());
  75 }