plat/imx/common/sci/imx8_mu.c

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <mmio.h>
   8 #include "imx8_mu.h"
   9
  10 void MU_EnableRxFullInt(uint32_t base, uint32_t index)
  11 {
  12         uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
  13
  14         reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
  15         reg |= MU_CR_RIE0_MASK1 >> index;
  16         mmio_write_32(base + MU_ACR_OFFSET1, reg);
  17 }
  18
  19 void MU_EnableGeneralInt(uint32_t base, uint32_t index)
  20 {
  21         uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
  22
  23         reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
  24         reg |= MU_CR_GIE0_MASK1 >> index;
  25         mmio_write_32(base + MU_ACR_OFFSET1, reg);
  26 }
  27
  28 void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg)
  29 {
  30         uint32_t mask = MU_SR_TE0_MASK1 >> regIndex;
  31
  32         /* Wait TX register to be empty. */
  33         while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
  34                 ;
  35         mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg);
  36 }
  37
  38 void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg)
  39 {
  40         uint32_t mask = MU_SR_RF0_MASK1 >> regIndex;
  41
  42         /* Wait RX register to be full. */
  43         while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
  44                 ;
  45         *msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4));
  46 }
  47
  48 void MU_Init(uint32_t base)
  49 {
  50         uint32_t reg;
  51
  52         reg = mmio_read_32(base + MU_ACR_OFFSET1);
  53         /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
  54         reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1
  55                         | MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1);
  56         mmio_write_32(base + MU_ACR_OFFSET1, reg);
  57 }