plat/imx/imx8qm/include/platform_def.h

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef PLATFORM_DEF_H
   8 #define PLATFORM_DEF_H
   9
  10 #include <utils_def.h>
  11
  12 #define PLATFORM_LINKER_FORMAT          "elf64-littleaarch64"
  13 #define PLATFORM_LINKER_ARCH            aarch64
  14
  15 #define PLATFORM_STACK_SIZE             0X400
  16 #define CACHE_WRITEBACK_GRANULE         64
  17
  18 #define PLAT_PRIMARY_CPU                0x0
  19 #define PLATFORM_MAX_CPU_PER_CLUSTER    4
  20 #define PLATFORM_CLUSTER_COUNT          2
  21 #define PLATFORM_CLUSTER0_CORE_COUNT    4
  22 #define PLATFORM_CLUSTER1_CORE_COUNT    2
  23 #define PLATFORM_CORE_COUNT             (PLATFORM_CLUSTER0_CORE_COUNT + \
  24                                          PLATFORM_CLUSTER1_CORE_COUNT)
  25
  26 #define IMX_PWR_LVL0                    MPIDR_AFFLVL0
  27 #define IMX_PWR_LVL1                    MPIDR_AFFLVL1
  28 #define IMX_PWR_LVL2                    MPIDR_AFFLVL2
  29
  30 #define PWR_DOMAIN_AT_MAX_LVL           U(1)
  31 #define PLAT_MAX_PWR_LVL                U(2)
  32 #define PLAT_MAX_OFF_STATE              U(2)
  33 #define PLAT_MAX_RET_STATE              U(1)
  34
  35 #define BL31_BASE                       0x80000000
  36 #define BL31_LIMIT                      0x80020000
  37
  38 #define PLAT_GICD_BASE                  0x51a00000
  39 #define PLAT_GICD_SIZE                  0x10000
  40 #define PLAT_GICR_BASE                  0x51b00000
  41 #define PLAT_GICR_SIZE                  0xc0000
  42 #define PLAT_CCI_BASE                   0x52090000
  43 #define PLAT_CCI_SIZE                   0x10000
  44 #define CLUSTER0_CCI_SLVAE_IFACE        3
  45 #define CLUSTER1_CCI_SLVAE_IFACE        4
  46 #define IMX_BOOT_UART_BASE              0x5a060000
  47 #define IMX_BOOT_UART_SIZE              0x1000
  48 #define IMX_BOOT_UART_BAUDRATE          115200
  49 #define IMX_BOOT_UART_CLK_IN_HZ         24000000
  50 #define PLAT_CRASH_UART_BASE            IMX_BOOT_UART_BASE
  51 #define PLAT__CRASH_UART_CLK_IN_HZ      24000000
  52 #define IMX_CONSOLE_BAUDRATE            115200
  53 #define SC_IPC_BASE                     0x5d1b0000
  54 #define SC_IPC_SIZE                     0x10000
  55
  56 #define COUNTER_FREQUENCY               8000000 /* 8MHz */
  57
  58 /* non-secure uboot base */
  59 #define PLAT_NS_IMAGE_OFFSET            0x80020000
  60
  61 #define PLAT_VIRT_ADDR_SPACE_SIZE       (1ull << 32)
  62 #define PLAT_PHY_ADDR_SPACE_SIZE        (1ull << 32)
  63
  64 #define MAX_XLAT_TABLES                 8
  65 #define MAX_MMAP_REGIONS                12
  66
  67 #define DEBUG_CONSOLE                   0
  68 #define DEBUG_CONSOLE_A53               0
  69 #define PLAT_IMX8QM                     1
  70
  71 #endif /* PLATFORM_DEF_H */