plat/marvell/a8k/a70x0/board/dram_port.c

   1 /*
   2  * Copyright (C) 2018 Marvell International Ltd.
   3  *
   4  * SPDX-License-Identifier:     BSD-3-Clause
   5  * https://spdx.org/licenses
   6  */
   7
   8 #include <arch_helpers.h>
   9 #include <debug.h>
  10 #include <mv_ddr_if.h>
  11 #include <plat_marvell.h>
  12
  13 /*
  14  * This function may modify the default DRAM parameters
  15  * based on information received from SPD or bootloader
  16  * configuration located on non volatile storage
  17  */
  18 void plat_marvell_dram_update_topology(void)
  19 {
  20 }
  21
  22 /*
  23  * This struct provides the DRAM training code with
  24  * the appropriate board DRAM configuration
  25  */
  26 static struct mv_ddr_topology_map board_topology_map = {
  27 /* FIXME: MISL board 2CS 4Gb x8 devices of micron - 2133P */
  28         DEBUG_LEVEL_ERROR,
  29         0x1, /* active interfaces */
  30         /* cs_mask, mirror, dqs_swap, ck_swap X subphys */
  31         { { { {0x3, 0x2, 0, 0},
  32               {0x3, 0x2, 0, 0},
  33               {0x3, 0x2, 0, 0},
  34               {0x3, 0x2, 0, 0},
  35               {0x3, 0x2, 0, 0},
  36               {0x3, 0x2, 0, 0},
  37               {0x3, 0x2, 0, 0},
  38               {0x3, 0x2, 0, 0},
  39               {0x3, 0x2, 0, 0} },
  40            SPEED_BIN_DDR_2133P,         /* speed_bin */
  41            MV_DDR_DEV_WIDTH_8BIT,       /* sdram device width */
  42            MV_DDR_DIE_CAP_4GBIT,        /* die capacity */
  43            MV_DDR_FREQ_SAR,             /* frequency */
  44            0, 0,                        /* cas_l, cas_wl */
  45            MV_DDR_TEMP_LOW} },          /* temperature */
  46         MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
  47         MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
  48         { {0} },                        /* raw spd data */
  49         {0},                            /* timing parameters */
  50         {                               /* electrical configuration */
  51                 {                       /* memory electrical configuration */
  52                         MV_DDR_RTT_NOM_PARK_RZQ_DISABLE,        /* rtt_nom */
  53                         {
  54                                 MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
  55                                 MV_DDR_RTT_NOM_PARK_RZQ_DIV1  /* rtt_park 2cs */
  56                         },
  57                         {
  58                                 MV_DDR_RTT_WR_DYN_ODT_OFF,      /* rtt_wr 1cs */
  59                                 MV_DDR_RTT_WR_RZQ_DIV2          /* rtt_wr 2cs */
  60                         },
  61                         MV_DDR_DIC_RZQ_DIV7     /* dic */
  62                 },
  63                 {                       /* phy electrical configuration */
  64                         MV_DDR_OHM_30,  /* data_drv_p */
  65                         MV_DDR_OHM_30,  /* data_drv_n */
  66                         MV_DDR_OHM_30,  /* ctrl_drv_p */
  67                         MV_DDR_OHM_30,  /* ctrl_drv_n */
  68                         {
  69                                 MV_DDR_OHM_60,  /* odt_p 1cs */
  70                                 MV_DDR_OHM_120  /* odt_p 2cs */
  71                         },
  72                         {
  73                                 MV_DDR_OHM_60,  /* odt_n 1cs */
  74                                 MV_DDR_OHM_120  /* odt_n 2cs */
  75                         },
  76                 },
  77                 {                       /* mac electrical configuration */
  78                         MV_DDR_ODT_CFG_NORMAL,          /* odtcfg_pattern */
  79                         MV_DDR_ODT_CFG_ALWAYS_ON,       /* odtcfg_write */
  80                         MV_DDR_ODT_CFG_NORMAL,          /* odtcfg_read */
  81                 },
  82         }
  83 };
  84
  85 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  86 {
  87         /* Return the board topology as defined in the board code */
  88         return &board_topology_map;
  89 }