plat/marvell/common/marvell_bl1_setup.c

   1 /*
   2  * Copyright (C) 2018 Marvell International Ltd.
   3  *
   4  * SPDX-License-Identifier:     BSD-3-Clause
   5  * https://spdx.org/licenses
   6  */
   7
   8 #include <platform_def.h>
   9
  10 #include <bl1/bl1.h>
  11 #include <bl1/bl1_private.h>
  12 #include <common/bl_common.h>
  13 #include <common/debug.h>
  14 #include <drivers/arm/sp805.h>
  15 #include <drivers/console.h>
  16 #include <plat/common/platform.h>
  17
  18 #include <plat_marvell.h>
  19
  20 /* Weak definitions may be overridden in specific Marvell standard platform */
  21 #pragma weak bl1_early_platform_setup
  22 #pragma weak bl1_plat_arch_setup
  23 #pragma weak bl1_platform_setup
  24 #pragma weak bl1_plat_sec_mem_layout
  25
  26 /* Data structure which holds the extents of the RAM for BL1*/
  27 static meminfo_t bl1_ram_layout;
  28
  29 meminfo_t *bl1_plat_sec_mem_layout(void)
  30 {
  31         return &bl1_ram_layout;
  32 }
  33
  34 /*
  35  * BL1 specific platform actions shared between Marvell standard platforms.
  36  */
  37 void marvell_bl1_early_platform_setup(void)
  38 {
  39         /* Initialize the console to provide early debug support */
  40         marvell_console_boot_init();
  41
  42         /* Allow BL1 to see the whole Trusted RAM */
  43         bl1_ram_layout.total_base = MARVELL_BL_RAM_BASE;
  44         bl1_ram_layout.total_size = MARVELL_BL_RAM_SIZE;
  45 }
  46
  47 void bl1_early_platform_setup(void)
  48 {
  49         marvell_bl1_early_platform_setup();
  50 }
  51
  52 /*
  53  * Perform the very early platform specific architecture setup shared between
  54  * MARVELL standard platforms. This only does basic initialization. Later
  55  * architectural setup (bl1_arch_setup()) does not do anything platform
  56  * specific.
  57  */
  58 void marvell_bl1_plat_arch_setup(void)
  59 {
  60         marvell_setup_page_tables(bl1_ram_layout.total_base,
  61                                   bl1_ram_layout.total_size,
  62                                   BL1_RO_BASE,
  63                                   BL1_RO_LIMIT,
  64                                   BL1_RO_DATA_BASE,
  65                                   BL1_RO_DATA_END
  66 #if USE_COHERENT_MEM
  67                                 , BL_COHERENT_RAM_BASE,
  68                                   BL_COHERENT_RAM_END
  69 #endif
  70                                 );
  71         enable_mmu_el3(0);
  72 }
  73
  74 void bl1_plat_arch_setup(void)
  75 {
  76         marvell_bl1_plat_arch_setup();
  77 }
  78
  79 /*
  80  * Perform the platform specific architecture setup shared between
  81  * MARVELL standard platforms.
  82  */
  83 void marvell_bl1_platform_setup(void)
  84 {
  85         /* Initialise the IO layer and register platform IO devices */
  86         plat_marvell_io_setup();
  87 }
  88
  89 void bl1_platform_setup(void)
  90 {
  91         marvell_bl1_platform_setup();
  92 }
  93
  94 void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
  95 {
  96 #ifdef EL3_PAYLOAD_BASE
  97         /*
  98          * Program the EL3 payload's entry point address into the CPUs mailbox
  99          * in order to release secondary CPUs from their holding pen and make
 100          * them jump there.
 101          */
 102         marvell_program_trusted_mailbox(ep_info->pc);
 103         dsbsy();
 104         sev();
 105 #endif
 106 }