plat/mediatek/mt6795/bl31.ld.S

   1 /*
   2  * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <platform_def.h>
   8 #include <xlat_tables_defs.h>
   9
  10 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
  11 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
  12 ENTRY(bl31_entrypoint)
  13
  14
  15 MEMORY {
  16         RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_TZRAM_SIZE
  17         RAM2 (rwx): ORIGIN = TZRAM2_BASE, LENGTH = TZRAM2_SIZE
  18 }
  19
  20
  21 SECTIONS
  22 {
  23     . = BL31_BASE;
  24
  25     ASSERT(. == ALIGN(2048),
  26            "vector base is not aligned on a 2K boundary.")
  27
  28     __RO_START__ = .;
  29     vector . : {
  30         *(.vectors)
  31     } >RAM
  32
  33     ASSERT(. == ALIGN(PAGE_SIZE),
  34            "BL31_BASE address is not aligned on a page boundary.")
  35
  36     ro . : {
  37         *bl31_entrypoint.o(.text*)
  38         *(.text*)
  39         *(.rodata*)
  40
  41         /* Ensure 8-byte alignment for descriptors and ensure inclusion */
  42         . = ALIGN(8);
  43         __RT_SVC_DESCS_START__ = .;
  44         KEEP(*(rt_svc_descs))
  45         __RT_SVC_DESCS_END__ = .;
  46
  47         /*
  48          * Ensure 8-byte alignment for cpu_ops so that its fields are also
  49          * aligned. Also ensure cpu_ops inclusion.
  50          */
  51         . = ALIGN(8);
  52         __CPU_OPS_START__ = .;
  53         KEEP(*(cpu_ops))
  54         __CPU_OPS_END__ = .;
  55
  56         __RO_END_UNALIGNED__ = .;
  57         /*
  58          * Memory page(s) mapped to this section will be marked as read-only,
  59          * executable.  No RW data from the next section must creep in.
  60          * Ensure the rest of the current memory page is unused.
  61          */
  62         . = NEXT(PAGE_SIZE);
  63         __RO_END__ = .;
  64     } >RAM
  65
  66     ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
  67            "cpu_ops not defined for this platform.")
  68
  69     /*
  70      * Define a linker symbol to mark start of the RW memory area for this
  71      * image.
  72      */
  73     __RW_START__ = . ;
  74
  75     /*
  76      * .data must be placed at a lower address than the stacks if the stack
  77      * protector is enabled. Alternatively, the .data.stack_protector_canary
  78      * section can be placed independently of the main .data section.
  79      */
  80     .data . : {
  81         __DATA_START__ = .;
  82         *(.data*)
  83         __DATA_END__ = .;
  84     } >RAM
  85
  86 #ifdef BL31_PROGBITS_LIMIT
  87     ASSERT(. <= BL31_PROGBITS_LIMIT, "BL3-1 progbits has exceeded its limit.")
  88 #endif
  89
  90     stacks (NOLOAD) : {
  91         __STACKS_START__ = .;
  92         *(tzfw_normal_stacks)
  93         __STACKS_END__ = .;
  94     } >RAM
  95
  96     /*
  97      * The .bss section gets initialised to 0 at runtime.
  98      * Its base address should be 16-byte aligned for better performance of the
  99      * zero-initialization code.
 100      */
 101     .bss (NOLOAD) : ALIGN(16) {
 102         __BSS_START__ = .;
 103         *(.bss*)
 104         *(COMMON)
 105 #if !USE_COHERENT_MEM
 106         /*
 107          * Bakery locks are stored in normal .bss memory
 108          *
 109          * Each lock's data is spread across multiple cache lines, one per CPU,
 110          * but multiple locks can share the same cache line.
 111          * The compiler will allocate enough memory for one CPU's bakery locks,
 112          * the remaining cache lines are allocated by the linker script
 113          */
 114         . = ALIGN(CACHE_WRITEBACK_GRANULE);
 115         __BAKERY_LOCK_START__ = .;
 116         *(bakery_lock)
 117         . = ALIGN(CACHE_WRITEBACK_GRANULE);
 118         __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
 119         . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
 120         __BAKERY_LOCK_END__ = .;
 121 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
 122     ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
 123         "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
 124 #endif
 125 #endif
 126         __BSS_END__ = .;
 127         __RW_END__ = .;
 128     } >RAM
 129
 130     ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.")
 131
 132     /*
 133      * The xlat_table section is for full, aligned page tables (4K).
 134      * Removing them from .bss avoids forcing 4K alignment on
 135      * the .bss section. The tables are initialized to zero by the translation
 136      * tables library.
 137      */
 138     xlat_table (NOLOAD) : {
 139         *(xlat_table)
 140     } >RAM2
 141
 142 #if USE_COHERENT_MEM
 143     /*
 144      * The base address of the coherent memory section must be page-aligned (4K)
 145      * to guarantee that the coherent data are stored on their own pages and
 146      * are not mixed with normal data.  This is required to set up the correct
 147      * memory attributes for the coherent data page tables.
 148      */
 149     coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
 150         __COHERENT_RAM_START__ = .;
 151         /*
 152          * Bakery locks are stored in coherent memory
 153          *
 154          * Each lock's data is contiguous and fully allocated by the compiler
 155          */
 156         *(bakery_lock)
 157         *(tzfw_coherent_mem)
 158         __COHERENT_RAM_END_UNALIGNED__ = .;
 159         /*
 160          * Memory page(s) mapped to this section will be marked
 161          * as device memory.  No other unexpected data must creep in.
 162          * Ensure the rest of the current memory page is unused.
 163          */
 164         . = NEXT(PAGE_SIZE);
 165         __COHERENT_RAM_END__ = .;
 166     } >RAM2
 167 #endif
 168
 169     /*
 170      * Define a linker symbol to mark end of the RW memory area for this
 171      * image.
 172      */
 173     __BL31_END__ = .;
 174
 175     __BSS_SIZE__ = SIZEOF(.bss);
 176 #if USE_COHERENT_MEM
 177     __COHERENT_RAM_UNALIGNED_SIZE__ =
 178         __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
 179 #endif
 180
 181     ASSERT(. <= TZRAM2_LIMIT, "TZRAM2 image has exceeded its limit.")
 182 }