plat/mediatek/mt8183/bl31_plat_setup.c

   1 /*
   2  * Copyright (c) 2019, MediaTek Inc. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8 #include <arch_helpers.h>
   9 #include <common/bl_common.h>
  10 #include <common/desc_image_load.h>
  11 #include <plat/common/common_def.h>
  12 #include <drivers/console.h>
  13 #include <common/debug.h>
  14 #include <drivers/generic_delay_timer.h>
  15 #include <mcucfg.h>
  16 #include <mt_gic_v3.h>
  17 #include <lib/coreboot.h>
  18 #include <lib/mmio.h>
  19 #include <mtk_plat_common.h>
  20 #include <mtspmc.h>
  21 #include <plat_debug.h>
  22 #include <plat_params.h>
  23 #include <plat_private.h>
  24 #include <platform_def.h>
  25 #include <scu.h>
  26 #include <spm.h>
  27 #include <drivers/ti/uart/uart_16550.h>
  28
  29 static entry_point_info_t bl32_ep_info;
  30 static entry_point_info_t bl33_ep_info;
  31
  32 static void platform_setup_cpu(void)
  33 {
  34         mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001);
  35
  36         /* Mcusys dcm control */
  37         /* Enable pll plldiv dcm */
  38         mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg,
  39                 BUS_PLLDIV_DCM);
  40         mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg,
  41                 MP0_PLLDIV_DCM);
  42         mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg,
  43                 MP2_PLLDIV_DCM);
  44         /* Enable mscib dcm  */
  45         mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en,
  46                 MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL);
  47         mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en,
  48                 MCSIB_DCM_MASK, MCSIB_DCM);
  49         /* Enable adb400 dcm */
  50         mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config,
  51                 CCI_ADB400_DCM_MASK, CCI_ADB400_DCM);
  52         /* Enable bus clock dcm */
  53         mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl,
  54                 MCU_BUS_DCM);
  55         /* Enable bus fabric dcm */
  56         mmio_clrsetbits_32(
  57                 (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl,
  58                 MCUSYS_BUS_FABRIC_DCM_MASK,
  59                 MCUSYS_BUS_FABRIC_DCM);
  60         /* Enable l2c sram dcm */
  61         mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl,
  62                 L2C_SRAM_DCM);
  63         /* Enable busmp0 sync dcm */
  64         mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config,
  65                 SYNC_DCM_MASK, SYNC_DCM);
  66         /* Enable cntvalue dcm */
  67         mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl,
  68                 CNTVALUEB_DCM);
  69         /* Enable dcm cluster stall */
  70         mmio_clrsetbits_32(
  71                 (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config,
  72                 MCUSYS_MAX_ACCESS_LATENCY_MASK,
  73                 MCUSYS_MAX_ACCESS_LATENCY);
  74         mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config,
  75                 MCU0_SYNC_DCM_STALL_WR_EN);
  76         /* Enable rgu dcm */
  77         mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config,
  78                 CPUSYS_RGU_DCM_CINFIG);
  79 }
  80
  81 /*******************************************************************************
  82  * Return a pointer to the 'entry_point_info' structure of the next image for
  83  * the security state specified. BL33 corresponds to the non-secure image type
  84  * while BL32 corresponds to the secure image type. A NULL pointer is returned
  85  * if the image does not exist.
  86  ******************************************************************************/
  87 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  88 {
  89         entry_point_info_t *next_image_info;
  90
  91         next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
  92         assert(next_image_info->h.type == PARAM_EP);
  93
  94         /* None of the images on this platform can have 0x0 as the entrypoint */
  95         if (next_image_info->pc)
  96                 return next_image_info;
  97         else
  98                 return NULL;
  99 }
 100
 101 /*******************************************************************************
 102  * Perform any BL31 early platform setup. Here is an opportunity to copy
 103  * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
 104  * are lost (potentially). This needs to be done before the MMU is initialized
 105  * so that the memory layout can be used while creating page tables.
 106  * BL2 has flushed this information to memory, so we are guaranteed to pick up
 107  * good data.
 108  ******************************************************************************/
 109 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 110                                 u_register_t arg2, u_register_t arg3)
 111 {
 112         static console_16550_t console;
 113
 114         params_early_setup(arg1);
 115
 116 #if COREBOOT
 117         if (coreboot_serial.type)
 118                 console_16550_register(coreboot_serial.baseaddr,
 119                                        coreboot_serial.input_hertz,
 120                                        coreboot_serial.baud,
 121                                        &console);
 122 #else
 123         console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
 124 #endif
 125
 126         NOTICE("MT8183 bl31_setup\n");
 127
 128         bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
 129 }
 130
 131
 132 /*******************************************************************************
 133  * Perform any BL31 platform setup code
 134  ******************************************************************************/
 135 void bl31_platform_setup(void)
 136 {
 137         platform_setup_cpu();
 138         generic_delay_timer_init();
 139
 140         /* Initialize the GIC driver, CPU and distributor interfaces */
 141         mt_gic_driver_init();
 142         mt_gic_init();
 143
 144         /* Init mcsi SF */
 145         plat_mtk_cci_init_sf();
 146
 147 #if SPMC_MODE == 1
 148         spmc_init();
 149 #endif
 150         spm_boot_init();
 151 }
 152
 153 /*******************************************************************************
 154  * Perform the very early platform specific architectural setup here. At the
 155  * moment this is only intializes the mmu in a quick and dirty way.
 156  ******************************************************************************/
 157 void bl31_plat_arch_setup(void)
 158 {
 159         plat_mtk_cci_init();
 160         plat_mtk_cci_enable();
 161
 162         enable_scu(read_mpidr());
 163
 164         plat_configure_mmu_el3(BL_CODE_BASE,
 165                                BL_COHERENT_RAM_END - BL_CODE_BASE,
 166                                BL_CODE_BASE,
 167                                BL_CODE_END,
 168                                BL_COHERENT_RAM_BASE,
 169                                BL_COHERENT_RAM_END);
 170 }