plat/mediatek/mt8183/include/plat_dcm.h

   1 /*
   2  * Copyright (c) 2019, MediaTek Inc. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef PLAT_DCM_H
   8 #define PLAT_DCM_H
   9
  10 #define MP2_SYNC_DCM            (MCUCFG_BASE + 0x2274)
  11 #define MP2_SYNC_DCM_MASK       (0x1 << 0)
  12 #define MP2_SYNC_DCM_ON         (0x1 << 0)
  13 #define MP2_SYNC_DCM_OFF        (0x0 << 0)
  14
  15 extern uint64_t plat_dcm_mcsi_a_addr;
  16 extern uint32_t plat_dcm_mcsi_a_val;
  17 extern int plat_dcm_initiated;
  18
  19 extern void plat_dcm_mcsi_a_backup(void);
  20 extern void plat_dcm_mcsi_a_restore(void);
  21 extern void plat_dcm_rgu_enable(void);
  22 extern void plat_dcm_restore_cluster_on(unsigned long mpidr);
  23 extern void plat_dcm_msg_handler(uint64_t x1);
  24 extern unsigned long plat_dcm_get_enabled_cnt(uint64_t type);
  25 extern void plat_dcm_init(void);
  26
  27 #define ALL_DCM_TYPE  (ARMCORE_DCM_TYPE | MCUSYS_DCM_TYPE \
  28                         | STALL_DCM_TYPE | BIG_CORE_DCM_TYPE \
  29                         | GIC_SYNC_DCM_TYPE | RGU_DCM_TYPE \
  30                         | INFRA_DCM_TYPE \
  31                         | DDRPHY_DCM_TYPE | EMI_DCM_TYPE | DRAMC_DCM_TYPE \
  32                         | MCSI_DCM_TYPE)
  33
  34 enum {
  35         ARMCORE_DCM_TYPE        = (1U << 0),
  36         MCUSYS_DCM_TYPE         = (1U << 1),
  37         INFRA_DCM_TYPE          = (1U << 2),
  38         PERI_DCM_TYPE           = (1U << 3),
  39         EMI_DCM_TYPE            = (1U << 4),
  40         DRAMC_DCM_TYPE          = (1U << 5),
  41         DDRPHY_DCM_TYPE         = (1U << 6),
  42         STALL_DCM_TYPE          = (1U << 7),
  43         BIG_CORE_DCM_TYPE       = (1U << 8),
  44         GIC_SYNC_DCM_TYPE       = (1U << 9),
  45         LAST_CORE_DCM_TYPE      = (1U << 10),
  46         RGU_DCM_TYPE            = (1U << 11),
  47         TOPCKG_DCM_TYPE         = (1U << 12),
  48         LPDMA_DCM_TYPE          = (1U << 13),
  49         MCSI_DCM_TYPE           = (1U << 14),
  50         NR_DCM_TYPE = 15,
  51 };
  52
  53 #endif /* PLAT_DCM_H */