plat/mediatek/mt8183/include/platform_def.h

   1 /*
   2  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef PLATFORM_DEF_H
   8 #define PLATFORM_DEF_H
   9
  10 #include <arch.h>
  11 #include <drivers/arm/gic_common.h>
  12
  13 #define PLAT_PRIMARY_CPU   0x0
  14
  15 #define IO_PHYS            0x10000000
  16 #define INFRACFG_AO_BASE   (IO_PHYS + 0x1000)
  17 #define PERI_BASE          (IO_PHYS + 0x3000)
  18 #define GPIO_BASE          (IO_PHYS + 0x5000)
  19 #define SPM_BASE           (IO_PHYS + 0x6000)
  20 #define SLEEP_REG_MD_BASE  (IO_PHYS + 0xf000)
  21 #define RGU_BASE           (IO_PHYS + 0x7000)
  22 #define I2C4_BASE_SE       (IO_PHYS + 0x1008000)
  23 #define I2C2_BASE_SE       (IO_PHYS + 0x1009000)
  24 #define PMIC_WRAP_BASE     (IO_PHYS + 0xd000)
  25 #define MCUCFG_BASE        0x0c530000
  26 #define CFG_SF_CTRL        0x0c510014
  27 #define CFG_SF_INI         0x0c510010
  28 #define EMI_MPU_BASE       (IO_PHYS + 0x226000)
  29 #define TRNG_base          (IO_PHYS + 0x20f000)
  30 #define MT_GIC_BASE        0x0c000000
  31 #define PLAT_MT_CCI_BASE   0x0c500000
  32 #define CCI_SIZE           0x00010000
  33 #define EINT_BASE          0x1000b000
  34 #define DVFSRC_BASE        (IO_PHYS + 0x12000)
  35
  36 #define SSPM_CFGREG_BASE   (IO_PHYS + 0x440000)
  37 #define SSPM_MBOX_3_BASE   (IO_PHYS + 0x480000)
  38
  39 #define INFRACFG_AO_BASE   (IO_PHYS + 0x1000)
  40
  41 #define APMIXEDSYS         (IO_PHYS + 0xC000)
  42 #define ARMPLL_LL_CON0     (APMIXEDSYS + 0x200)
  43 #define ARMPLL_L_CON0      (APMIXEDSYS + 0x210)
  44 #define ARMPLL_L_PWR_CON0  (APMIXEDSYS + 0x21c)
  45 #define MAINPLL_CON0       (APMIXEDSYS + 0x220)
  46 #define CCIPLL_CON0        (APMIXEDSYS + 0x290)
  47
  48 #define TOP_CKMUXSEL       (INFRACFG_AO_BASE + 0x0)
  49
  50 #define armpll_mux1_sel_big_mask    (0xf << 4)
  51 #define armpll_mux1_sel_big_ARMSPLL (0x1 << 4)
  52 #define armpll_mux1_sel_sml_mask    (0xf << 8)
  53 #define armpll_mux1_sel_sml_ARMSPLL (0x1 << 8)
  54
  55
  56 /* Aggregate of all devices in the first GB */
  57 #define MTK_DEV_RNG0_BASE    IO_PHYS
  58 #define MTK_DEV_RNG0_SIZE    0x490000
  59 #define MTK_DEV_RNG1_BASE    (IO_PHYS + 0x1000000)
  60 #define MTK_DEV_RNG1_SIZE    0x4000000
  61 #define MTK_DEV_RNG2_BASE    0x0c000000
  62 #define MTK_DEV_RNG2_SIZE    0x600000
  63 #define MT_MCUSYS_SIZE       0x90000
  64 #define RAM_CONSOLE_BASE     0x11d000
  65 #define RAM_CONSOLE_SIZE     0x1000
  66
  67 /*******************************************************************************
  68  * MSDC
  69  ******************************************************************************/
  70 #define MSDC0_BASE          (IO_PHYS + 0x01230000)
  71
  72 /*******************************************************************************
  73  * MCUSYS related constants
  74  ******************************************************************************/
  75 #define MT_L2_WRITE_ACCESS_RATE  (MCUCFG_BASE + 0x604)
  76 #define MP0_CA7L_CACHE_CONFIG    (MCUCFG_BASE + 0x7f0)
  77 #define MP1_CA7L_CACHE_CONFIG    (MCUCFG_BASE + 0x7f4)
  78 #define EMI_WFIFO                (MCUCFG_BASE + 0x0b5c)
  79
  80 /*******************************************************************************
  81  * GIC related constants
  82  ******************************************************************************/
  83 #define MT_POLARITY_LOW     0
  84 #define MT_POLARITY_HIGH    1
  85 #define MT_EDGE_SENSITIVE   1
  86 #define MT_LEVEL_SENSITIVE  0
  87
  88 /*******************************************************************************
  89  * UART related constants
  90  ******************************************************************************/
  91 #define UART0_BASE    (IO_PHYS + 0x01002000)
  92 #define UART1_BASE    (IO_PHYS + 0x01003000)
  93
  94 #define UART_BAUDRATE 115200
  95 #define UART_CLOCK    26000000
  96
  97 /*******************************************************************************
  98  * System counter frequency related constants
  99  ******************************************************************************/
 100 #define SYS_COUNTER_FREQ_IN_TICKS    13000000
 101 #define SYS_COUNTER_FREQ_IN_MHZ      13
 102
 103 /*******************************************************************************
 104  * GIC-400 & interrupt handling related constants
 105  ******************************************************************************/
 106
 107 /* Base MTK_platform compatible GIC memory map */
 108 #define BASE_GICD_BASE        MT_GIC_BASE
 109 #define BASE_GICC_BASE        (MT_GIC_BASE + 0x400000)
 110 #define MT_GIC_RDIST_BASE     (MT_GIC_BASE + 0x100000)
 111 #define BASE_GICR_BASE        (MT_GIC_BASE + 0x100000)
 112 #define BASE_GICH_BASE        (MT_GIC_BASE + 0x4000)
 113 #define BASE_GICV_BASE        (MT_GIC_BASE + 0x6000)
 114 #define INT_POL_CTL0          (MCUCFG_BASE + 0xa80)
 115 #define SEC_POL_CTL_EN0       (MCUCFG_BASE + 0xa00)
 116 #define GIC_SYNC_DCM          (MCUCFG_BASE + 0x758)
 117 #define GIC_SYNC_DCM_MASK     0x3
 118 #define GIC_SYNC_DCM_ON       0x3
 119 #define GIC_SYNC_DCM_OFF      0x0
 120 #define GIC_PRIVATE_SIGNALS   32
 121
 122 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
 123 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE
 124
 125 #define PLAT_ARM_G1S_IRQ_PROPS(grp) ( \
 126 INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
 127                         GIC_INTR_CFG_EDGE), \
 128 INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
 129                         GIC_INTR_CFG_EDGE), \
 130 INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
 131                         GIC_INTR_CFG_EDGE), \
 132 INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
 133                         GIC_INTR_CFG_EDGE), \
 134 INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
 135                         GIC_INTR_CFG_EDGE), \
 136 INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
 137                         GIC_INTR_CFG_EDGE), \
 138 INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
 139                         GIC_INTR_CFG_EDGE), \
 140 INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
 141                         GIC_INTR_CFG_EDGE)) \
 142
 143 #define PLAT_ARM_G0_IRQ_PROPS(grp)
 144
 145 /*******************************************************************************
 146  * CCI-400 related constants
 147  ******************************************************************************/
 148 #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX    4
 149 #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX    3
 150
 151 /*******************************************************************************
 152  * WDT Registers
 153  ******************************************************************************/
 154 #define MTK_WDT_BASE            (IO_PHYS + 0x00007000)
 155 #define MTK_WDT_SIZE            0x1000
 156 #define MTK_WDT_MODE            (MTK_WDT_BASE + 0x0000)
 157 #define MTK_WDT_LENGTH          (MTK_WDT_BASE + 0x0004)
 158 #define MTK_WDT_RESTART         (MTK_WDT_BASE + 0x0008)
 159 #define MTK_WDT_STATUS          (MTK_WDT_BASE + 0x000C)
 160 #define MTK_WDT_INTERVAL        (MTK_WDT_BASE + 0x0010)
 161 #define MTK_WDT_SWRST           (MTK_WDT_BASE + 0x0014)
 162 #define MTK_WDT_SWSYSRST        (MTK_WDT_BASE + 0x0018)
 163 #define MTK_WDT_NONRST_REG      (MTK_WDT_BASE + 0x0020)
 164 #define MTK_WDT_NONRST_REG2     (MTK_WDT_BASE + 0x0024)
 165 #define MTK_WDT_REQ_MODE        (MTK_WDT_BASE + 0x0030)
 166 #define MTK_WDT_REQ_IRQ_EN      (MTK_WDT_BASE + 0x0034)
 167 #define MTK_WDT_EXT_REQ_CON     (MTK_WDT_BASE + 0x0038)
 168 #define MTK_WDT_DEBUG_CTL       (MTK_WDT_BASE + 0x0040)
 169 #define MTK_WDT_LATCH_CTL       (MTK_WDT_BASE + 0x0044)
 170 #define MTK_WDT_DEBUG_CTL2      (MTK_WDT_BASE + 0x00A0)
 171 #define MTK_WDT_COUNTER         (MTK_WDT_BASE + 0x0514)
 172
 173 /* WDT_STATUS */
 174 #define MTK_WDT_STATUS_SPM_THERMAL_RST      (1 << 0)
 175 #define MTK_WDT_STATUS_SPM_RST              (1 << 1)
 176 #define MTK_WDT_STATUS_EINT_RST             (1 << 2)
 177 #define MTK_WDT_STATUS_SYSRST_RST           (1 << 3) /* from PMIC */
 178 #define MTK_WDT_STATUS_DVFSP_RST            (1 << 4)
 179 #define MTK_WDT_STATUS_PMCU_RST             (1 << 16)
 180 #define MTK_WDT_STATUS_MDDBG_RST            (1 << 17)
 181 #define MTK_WDT_STATUS_THERMAL_DIRECT_RST   (1 << 18)
 182 #define MTK_WDT_STATUS_DEBUG_RST            (1 << 19)
 183 #define MTK_WDT_STATUS_SECURITY_RST         (1 << 28)
 184 #define MTK_WDT_STATUS_IRQ_ASSERT           (1 << 29)
 185 #define MTK_WDT_STATUS_SW_WDT_RST           (1 << 30)
 186 #define MTK_WDT_STATUS_HW_WDT_RST           (1U << 31)
 187
 188 /* RGU other related */
 189 #define MTK_WDT_MODE_DUAL_MODE    0x0040
 190 #define MTK_WDT_MODE_IRQ          0x0008
 191 #define MTK_WDT_MODE_KEY          0x22000000
 192 #define MTK_WDT_MODE_EXTEN        0x0004
 193 #define MTK_WDT_SWRST_KEY         0x1209
 194 #define MTK_WDT_RESTART_KEY       0x1971
 195
 196 /*******************************************************************************
 197  * TRNG Registers
 198  ******************************************************************************/
 199 #define TRNG_BASE_ADDR       TRNG_base
 200 #define TRNG_BASE_SIZE       0x1000
 201 #define TRNG_CTRL            (TRNG_base + 0x0000)
 202 #define TRNG_TIME            (TRNG_base + 0x0004)
 203 #define TRNG_DATA            (TRNG_base + 0x0008)
 204 #define TRNG_PDN_base        0x10001000
 205 #define TRNG_PDN_BASE_ADDR   TRNG_PDN_BASE_ADDR
 206 #define TRNG_PDN_BASE_SIZE   0x1000
 207 #define TRNG_PDN_SET         (TRNG_PDN_base + 0x0088)
 208 #define TRNG_PDN_CLR         (TRNG_PDN_base + 0x008c)
 209 #define TRNG_PDN_STATUS      (TRNG_PDN_base + 0x0094)
 210 #define TRNG_CTRL_RDY        0x80000000
 211 #define TRNG_CTRL_START      0x00000001
 212 #define TRNG_PDN_VALUE       0x200
 213
 214 /* FIQ platform related define */
 215 #define MT_IRQ_SEC_SGI_0    8
 216 #define MT_IRQ_SEC_SGI_1    9
 217 #define MT_IRQ_SEC_SGI_2    10
 218 #define MT_IRQ_SEC_SGI_3    11
 219 #define MT_IRQ_SEC_SGI_4    12
 220 #define MT_IRQ_SEC_SGI_5    13
 221 #define MT_IRQ_SEC_SGI_6    14
 222 #define MT_IRQ_SEC_SGI_7    15
 223
 224 #define FIQ_SMP_CALL_SGI    13
 225 #define WDT_IRQ_BIT_ID      174
 226 #define ATF_LOG_IRQ_ID      277
 227
 228 #define ATF_AMMS_IRQ_ID     338
 229 #define PCCIF1_IRQ0_BIT_ID  185
 230 #define PCCIF1_IRQ1_BIT_ID  186
 231
 232 #define DEBUG_XLAT_TABLE    0
 233
 234 /*******************************************************************************
 235  * Platform binary types for linking
 236  ******************************************************************************/
 237 #define PLATFORM_LINKER_FORMAT      "elf64-littleaarch64"
 238 #define PLATFORM_LINKER_ARCH        aarch64
 239
 240 /*******************************************************************************
 241  * Generic platform constants
 242  ******************************************************************************/
 243
 244 /* Size of cacheable stacks */
 245 #if DEBUG_XLAT_TABLE
 246 #define PLATFORM_STACK_SIZE    0x800
 247 #elif IMAGE_BL1
 248 #define PLATFORM_STACK_SIZE    0x440
 249 #elif IMAGE_BL2
 250 #define PLATFORM_STACK_SIZE    0x400
 251 #elif IMAGE_BL31
 252 #define PLATFORM_STACK_SIZE    0x800
 253 #elif IMAGE_BL32
 254 #define PLATFORM_STACK_SIZE    0x440
 255 #endif
 256
 257 #define FIRMWARE_WELCOME_STR    "Booting Trusted Firmware\n"
 258 #define PLAT_MAX_PWR_LVL        U(2)
 259 #define PLAT_MAX_RET_STATE              U(1)
 260 #define PLAT_MAX_OFF_STATE              U(2)
 261
 262 #define PLATFORM_CACHE_LINE_SIZE        64
 263 #define PLATFORM_SYSTEM_COUNT           1
 264 #define PLATFORM_CLUSTER_COUNT          2
 265 #define PLATFORM_CLUSTER0_CORE_COUNT    4
 266 #define PLATFORM_CLUSTER1_CORE_COUNT    4
 267 #define PLATFORM_CORE_COUNT             (PLATFORM_CLUSTER1_CORE_COUNT + \
 268                                          PLATFORM_CLUSTER0_CORE_COUNT)
 269 #define PLATFORM_MAX_CPUS_PER_CLUSTER   4
 270 #define PLATFORM_NUM_AFFS               (PLATFORM_SYSTEM_COUNT + \
 271                                          PLATFORM_CLUSTER_COUNT + \
 272                                          PLATFORM_CORE_COUNT)
 273
 274 /*******************************************************************************
 275  * Platform memory map related constants
 276  ******************************************************************************/
 277
 278 #define TZRAM_BASE          0x54600000
 279 #define TZRAM_SIZE          0x00030000
 280
 281 /*******************************************************************************
 282  * BL31 specific defines.
 283  ******************************************************************************/
 284 /*
 285  * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
 286  * present). BL31_BASE is calculated using the current BL31 debug size plus a
 287  * little space for growth.
 288  */
 289 #define BL31_BASE       (TZRAM_BASE + 0x1000)
 290 #define BL31_LIMIT      (TZRAM_BASE + TZRAM_SIZE)
 291
 292 /*******************************************************************************
 293  * Platform specific page table and MMU setup constants
 294  ******************************************************************************/
 295 #define PLAT_PHY_ADDR_SPACE_SIZE    (1ULL << 32)
 296 #define PLAT_VIRT_ADDR_SPACE_SIZE   (1ULL << 32)
 297 #define MAX_XLAT_TABLES             16
 298 #define MAX_MMAP_REGIONS            16
 299
 300 /*******************************************************************************
 301  * Declarations and constants to access the mailboxes safely. Each mailbox is
 302  * aligned on the biggest cache line size in the platform. This is known only
 303  * to the platform as it might have a combination of integrated and external
 304  * caches. Such alignment ensures that two maiboxes do not sit on the same cache
 305  * line at any cache level. They could belong to different cpus/clusters &
 306  * get written while being protected by different locks causing corruption of
 307  * a valid mailbox address.
 308  ******************************************************************************/
 309 #define CACHE_WRITEBACK_SHIFT    6
 310 #define CACHE_WRITEBACK_GRANULE  (1 << CACHE_WRITEBACK_SHIFT)
 311 #endif /* PLATFORM_DEF_H */