plat/nvidia/tegra/common/drivers/smmu/smmu.c

   1 /*
   2  * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8 #include <bl_common.h>
   9 #include <debug.h>
  10 #include <platform_def.h>
  11 #include <smmu.h>
  12 #include <string.h>
  13 #include <tegra_private.h>
  14
  15 extern void memcpy16(void *dest, const void *src, unsigned int length);
  16
  17 /* SMMU IDs currently supported by the driver */
  18 enum {
  19         TEGRA_SMMU0,
  20         TEGRA_SMMU1,
  21         TEGRA_SMMU2
  22 };
  23
  24 static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
  25 {
  26 #if defined(TEGRA_SMMU0_BASE)
  27         if (smmu_id == TEGRA_SMMU0)
  28                 return mmio_read_32(TEGRA_SMMU0_BASE + off);
  29 #endif
  30
  31 #if defined(TEGRA_SMMU1_BASE)
  32         if (smmu_id == TEGRA_SMMU1)
  33                 return mmio_read_32(TEGRA_SMMU1_BASE + off);
  34 #endif
  35
  36 #if defined(TEGRA_SMMU2_BASE)
  37         if (smmu_id == TEGRA_SMMU2)
  38                 return mmio_read_32(TEGRA_SMMU2_BASE + off);
  39 #endif
  40
  41         return 0;
  42 }
  43
  44 static void tegra_smmu_write_32(uint32_t smmu_id,
  45                         uint32_t off, uint32_t val)
  46 {
  47 #if defined(TEGRA_SMMU0_BASE)
  48         if (smmu_id == TEGRA_SMMU0)
  49                 mmio_write_32(TEGRA_SMMU0_BASE + off, val);
  50 #endif
  51
  52 #if defined(TEGRA_SMMU1_BASE)
  53         if (smmu_id == TEGRA_SMMU1)
  54                 mmio_write_32(TEGRA_SMMU1_BASE + off, val);
  55 #endif
  56
  57 #if defined(TEGRA_SMMU2_BASE)
  58         if (smmu_id == TEGRA_SMMU2)
  59                 mmio_write_32(TEGRA_SMMU2_BASE + off, val);
  60 #endif
  61 }
  62
  63 /*
  64  * Save SMMU settings before "System Suspend" to TZDRAM
  65  */
  66 void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
  67 {
  68         uint32_t i, num_entries = 0;
  69         smmu_regs_t *smmu_ctx_regs;
  70         plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
  71         uint64_t tzdram_base = params_from_bl2->tzdram_base;
  72         uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
  73         uint32_t reg_id1, pgshift, cb_size;
  74
  75         /* sanity check SMMU settings c*/
  76         reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
  77         pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12;
  78         cb_size = (2 << pgshift) * \
  79         (1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
  80
  81         assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
  82         assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
  83
  84         /* get SMMU context table */
  85         smmu_ctx_regs = plat_get_smmu_ctx();
  86         assert(smmu_ctx_regs);
  87
  88         /*
  89          * smmu_ctx_regs[0].val contains the size of the context table minus
  90          * the last entry. Sanity check the table size before we start with
  91          * the context save operation.
  92          */
  93         while (smmu_ctx_regs[num_entries].val != 0xFFFFFFFFU) {
  94                 num_entries++;
  95         }
  96
  97         /* panic if the sizes do not match */
  98         if (num_entries != smmu_ctx_regs[0].val)
  99                 panic();
 100
 101         /* save SMMU register values */
 102         for (i = 1; i < num_entries; i++)
 103                 smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
 104
 105         /* increment by 1 to take care of the last entry */
 106         num_entries++;
 107
 108         /* Save SMMU config settings */
 109         memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs,
 110                  (sizeof(smmu_regs_t) * num_entries));
 111
 112         /* save the SMMU table address */
 113         mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO,
 114                 (uint32_t)smmu_ctx_addr);
 115         mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI,
 116                 (uint32_t)(smmu_ctx_addr >> 32));
 117 }
 118
 119 #define SMMU_NUM_CONTEXTS               64
 120 #define SMMU_CONTEXT_BANK_MAX_IDX       64
 121
 122 /*
 123  * Init SMMU during boot or "System Suspend" exit
 124  */
 125 void tegra_smmu_init(void)
 126 {
 127         uint32_t val, cb_idx, smmu_id, ctx_base;
 128
 129         for (smmu_id = 0; smmu_id < NUM_SMMU_DEVICES; smmu_id++) {
 130                 /* Program the SMMU pagesize and reset CACHE_LOCK bit */
 131                 val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
 132                 val |= SMMU_GSR0_PGSIZE_64K;
 133                 val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
 134                 tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
 135
 136                 /* reset CACHE LOCK bit for NS Aux. Config. Register */
 137                 val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
 138                 val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
 139                 tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
 140
 141                 /* disable TCU prefetch for all contexts */
 142                 ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS)
 143                                 + SMMU_CBn_ACTLR;
 144                 for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
 145                         val = tegra_smmu_read_32(smmu_id,
 146                                 ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
 147                         val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
 148                         tegra_smmu_write_32(smmu_id, ctx_base +
 149                                 (SMMU_GSR0_PGSIZE_64K * cb_idx), val);
 150                 }
 151
 152                 /* set CACHE LOCK bit for NS Aux. Config. Register */
 153                 val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
 154                 val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
 155                 tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
 156
 157                 /* set CACHE LOCK bit for S Aux. Config. Register */
 158                 val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
 159                 val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
 160                 tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
 161         }
 162 }