plat/nvidia/tegra/soc/t132/plat_psci_handlers.c

   1 /*
   2  * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch.h>
   8 #include <arch_helpers.h>
   9 #include <assert.h>
  10 #include <debug.h>
  11 #include <delay_timer.h>
  12 #include <denver.h>
  13 #include <flowctrl.h>
  14 #include <mmio.h>
  15 #include <platform_def.h>
  16 #include <pmc.h>
  17 #include <psci.h>
  18 #include <tegra_def.h>
  19 #include <tegra_private.h>
  20
  21 /*
  22  * Register used to clear CPU reset signals. Each CPU has two reset
  23  * signals: CPU reset (3:0) and Core reset (19:16)
  24  */
  25 #define CPU_CMPLX_RESET_CLR             0x344
  26 #define CPU_CORE_RESET_MASK             0x10001
  27
  28 /* Clock and Reset controller registers for system clock's settings */
  29 #define SCLK_RATE                       0x30
  30 #define SCLK_BURST_POLICY               0x28
  31 #define SCLK_BURST_POLICY_DEFAULT       0x10000000
  32
  33 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
  34
  35 int32_t tegra_soc_validate_power_state(unsigned int power_state,
  36                                         psci_power_state_t *req_state)
  37 {
  38         int state_id = psci_get_pstate_id(power_state);
  39         int cpu = read_mpidr() & MPIDR_CPU_MASK;
  40
  41         /*
  42          * Sanity check the requested state id, power level and CPU number.
  43          * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU
  44          * i.e. CPU 0
  45          */
  46         if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) {
  47                 ERROR("unsupported state id @ power level\n");
  48                 return PSCI_E_INVALID_PARAMS;
  49         }
  50
  51         /* Set lower power states to PLAT_MAX_OFF_STATE */
  52         for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
  53                 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
  54
  55         /* Set the SYSTEM_SUSPEND state-id */
  56         req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
  57                 PSTATE_ID_SOC_POWERDN;
  58
  59         return PSCI_E_SUCCESS;
  60 }
  61
  62 int tegra_soc_pwr_domain_on(u_register_t mpidr)
  63 {
  64         int cpu = mpidr & MPIDR_CPU_MASK;
  65         uint32_t mask = CPU_CORE_RESET_MASK << cpu;
  66
  67         if (cpu_powergate_mask[cpu] == 0) {
  68
  69                 /* Deassert CPU reset signals */
  70                 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
  71
  72                 /* Power on CPU using PMC */
  73                 tegra_pmc_cpu_on(cpu);
  74
  75                 /* Fill in the CPU powergate mask */
  76                 cpu_powergate_mask[cpu] = 1;
  77
  78         } else {
  79                 /* Power on CPU using Flow Controller */
  80                 tegra_fc_cpu_on(cpu);
  81         }
  82
  83         return PSCI_E_SUCCESS;
  84 }
  85
  86 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
  87 {
  88         /*
  89          * Lock scratch registers which hold the CPU vectors
  90          */
  91         tegra_pmc_lock_cpu_vectors();
  92
  93         return PSCI_E_SUCCESS;
  94 }
  95
  96 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
  97 {
  98         tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
  99
 100         /* Disable DCO operations */
 101         denver_disable_dco();
 102
 103         /* Power down the CPU */
 104         write_actlr_el1(DENVER_CPU_STATE_POWER_DOWN);
 105
 106         return PSCI_E_SUCCESS;
 107 }
 108
 109 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 110 {
 111 #if ENABLE_ASSERTIONS
 112         int cpu = read_mpidr() & MPIDR_CPU_MASK;
 113
 114         /* SYSTEM_SUSPEND only on CPU0 */
 115         assert(cpu == 0);
 116 #endif
 117
 118         /* Allow restarting CPU #1 using PMC on suspend exit */
 119         cpu_powergate_mask[1] = 0;
 120
 121         /* Program FC to enter suspend state */
 122         tegra_fc_cpu_powerdn(read_mpidr());
 123
 124         /* Disable DCO operations */
 125         denver_disable_dco();
 126
 127         /* Program the suspend state ID */
 128         write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
 129
 130         return PSCI_E_SUCCESS;
 131 }
 132
 133 int tegra_soc_prepare_system_reset(void)
 134 {
 135         /*
 136          * Set System Clock (SCLK) to POR default so that the clock source
 137          * for the PMC APB clock would not be changed due to system reset.
 138          */
 139         mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY,
 140                        SCLK_BURST_POLICY_DEFAULT);
 141         mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0);
 142
 143         /* Wait 1 ms to make sure clock source/device logic is stabilized. */
 144         mdelay(1);
 145
 146         return PSCI_E_SUCCESS;
 147 }