plat/nvidia/tegra/soc/t186/drivers/mce/ari.c

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch.h>
   8 #include <arch_helpers.h>
   9 #include <assert.h>
  10 #include <debug.h>
  11 #include <delay_timer.h>
  12 #include <denver.h>
  13 #include <errno.h>
  14 #include <mce_private.h>
  15 #include <mmio.h>
  16 #include <platform.h>
  17 #include <t18x_ari.h>
  18
  19 /*******************************************************************************
  20  * Register offsets for ARI request/results
  21  ******************************************************************************/
  22 #define ARI_REQUEST                     0x0U
  23 #define ARI_REQUEST_EVENT_MASK          0x4U
  24 #define ARI_STATUS                      0x8U
  25 #define ARI_REQUEST_DATA_LO             0xCU
  26 #define ARI_REQUEST_DATA_HI             0x10U
  27 #define ARI_RESPONSE_DATA_LO            0x14U
  28 #define ARI_RESPONSE_DATA_HI            0x18U
  29
  30 /* Status values for the current request */
  31 #define ARI_REQ_PENDING                 1U
  32 #define ARI_REQ_ONGOING                 3U
  33 #define ARI_REQUEST_VALID_BIT           (1U << 8)
  34 #define ARI_EVT_MASK_STANDBYWFI_BIT     (1U << 7)
  35
  36 /* default timeout (ms) to wait for ARI completion */
  37 #define ARI_MAX_RETRY_COUNT             2000
  38
  39 /*******************************************************************************
  40  * ARI helper functions
  41  ******************************************************************************/
  42 static inline uint32_t ari_read_32(uint32_t ari_base, uint32_t reg)
  43 {
  44         return mmio_read_32((uint64_t)ari_base + (uint64_t)reg);
  45 }
  46
  47 static inline void ari_write_32(uint32_t ari_base, uint32_t val, uint32_t reg)
  48 {
  49         mmio_write_32((uint64_t)ari_base + (uint64_t)reg, val);
  50 }
  51
  52 static inline uint32_t ari_get_request_low(uint32_t ari_base)
  53 {
  54         return ari_read_32(ari_base, ARI_REQUEST_DATA_LO);
  55 }
  56
  57 static inline uint32_t ari_get_request_high(uint32_t ari_base)
  58 {
  59         return ari_read_32(ari_base, ARI_REQUEST_DATA_HI);
  60 }
  61
  62 static inline uint32_t ari_get_response_low(uint32_t ari_base)
  63 {
  64         return ari_read_32(ari_base, ARI_RESPONSE_DATA_LO);
  65 }
  66
  67 static inline uint32_t ari_get_response_high(uint32_t ari_base)
  68 {
  69         return ari_read_32(ari_base, ARI_RESPONSE_DATA_HI);
  70 }
  71
  72 static inline void ari_clobber_response(uint32_t ari_base)
  73 {
  74         ari_write_32(ari_base, 0, ARI_RESPONSE_DATA_LO);
  75         ari_write_32(ari_base, 0, ARI_RESPONSE_DATA_HI);
  76 }
  77
  78 static int32_t ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req,
  79                 uint32_t lo, uint32_t hi)
  80 {
  81         uint32_t retries = ARI_MAX_RETRY_COUNT;
  82         uint32_t status;
  83         int32_t ret = 0;
  84
  85         /* program the request, event_mask, hi and lo registers */
  86         ari_write_32(ari_base, lo, ARI_REQUEST_DATA_LO);
  87         ari_write_32(ari_base, hi, ARI_REQUEST_DATA_HI);
  88         ari_write_32(ari_base, evt_mask, ARI_REQUEST_EVENT_MASK);
  89         ari_write_32(ari_base, req | ARI_REQUEST_VALID_BIT, ARI_REQUEST);
  90
  91         /*
  92          * For commands that have an event trigger, we should bypass
  93          * ARI_STATUS polling, since MCE is waiting for SW to trigger
  94          * the event.
  95          */
  96         if (evt_mask != 0U) {
  97                 ret = 0;
  98         } else {
  99                 /* For shutdown/reboot commands, we dont have to check for timeouts */
 100                 if ((req == (uint32_t)TEGRA_ARI_MISC_CCPLEX) &&
 101                     ((lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) ||
 102                      (lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) {
 103                                 ret = 0;
 104                 } else {
 105                         /*
 106                          * Wait for the command response for not more than the timeout
 107                          */
 108                         while (retries != 0U) {
 109
 110                                 /* read the command status */
 111                                 status = ari_read_32(ari_base, ARI_STATUS);
 112                                 if ((status & (ARI_REQ_ONGOING | ARI_REQ_PENDING)) == 0U) {
 113                                         break;
 114                                 }
 115
 116                                 /* delay 1 ms */
 117                                 mdelay(1);
 118
 119                                 /* decrement the retry count */
 120                                 retries--;
 121                         }
 122
 123                         /* assert if the command timed out */
 124                         if (retries == 0U) {
 125                                 ERROR("ARI request timed out: req %d on CPU %d\n",
 126                                         req, plat_my_core_pos());
 127                                 assert(retries != 0U);
 128                         }
 129                 }
 130         }
 131
 132         return ret;
 133 }
 134
 135 int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
 136 {
 137         int32_t ret = 0;
 138
 139         /* check for allowed power state */
 140         if ((state != TEGRA_ARI_CORE_C0) &&
 141             (state != TEGRA_ARI_CORE_C1) &&
 142             (state != TEGRA_ARI_CORE_C6) &&
 143             (state != TEGRA_ARI_CORE_C7)) {
 144                 ERROR("%s: unknown cstate (%d)\n", __func__, state);
 145                 ret = EINVAL;
 146         } else {
 147                 /* clean the previous response state */
 148                 ari_clobber_response(ari_base);
 149
 150                 /* Enter the cstate, to be woken up after wake_time (TSC ticks) */
 151                 ret = ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT,
 152                 TEGRA_ARI_ENTER_CSTATE, state, wake_time);
 153         }
 154
 155         return ret;
 156 }
 157
 158 int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
 159         uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
 160         uint8_t update_wake_mask)
 161 {
 162         uint32_t val = 0U;
 163
 164         /* clean the previous response state */
 165         ari_clobber_response(ari_base);
 166
 167         /* update CLUSTER_CSTATE? */
 168         if (cluster != 0U) {
 169                 val |= (cluster & (uint32_t)CLUSTER_CSTATE_MASK) |
 170                         (uint32_t)CLUSTER_CSTATE_UPDATE_BIT;
 171         }
 172
 173         /* update CCPLEX_CSTATE? */
 174         if (ccplex != 0U) {
 175                 val |= ((ccplex & (uint32_t)CCPLEX_CSTATE_MASK) << (uint32_t)CCPLEX_CSTATE_SHIFT) |
 176                         (uint32_t)CCPLEX_CSTATE_UPDATE_BIT;
 177         }
 178
 179         /* update SYSTEM_CSTATE? */
 180         if (system != 0U) {
 181                 val |= ((system & (uint32_t)SYSTEM_CSTATE_MASK) << (uint32_t)SYSTEM_CSTATE_SHIFT) |
 182                        (((uint32_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
 183                         (uint32_t)SYSTEM_CSTATE_UPDATE_BIT);
 184         }
 185
 186         /* update wake mask value? */
 187         if (update_wake_mask != 0U) {
 188                 val |= (uint32_t)CSTATE_WAKE_MASK_UPDATE_BIT;
 189         }
 190
 191         /* set the updated cstate info */
 192         return ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CSTATE_INFO, val,
 193                         wake_mask);
 194 }
 195
 196 int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time)
 197 {
 198         int32_t ret = 0;
 199
 200         /* sanity check crossover type */
 201         if ((type == TEGRA_ARI_CROSSOVER_C1_C6) ||
 202             (type > TEGRA_ARI_CROSSOVER_CCP3_SC1)) {
 203                 ret = EINVAL;
 204         } else {
 205                 /* clean the previous response state */
 206                 ari_clobber_response(ari_base);
 207
 208                 /* update crossover threshold time */
 209                 ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CROSSOVER,
 210                         type, time);
 211         }
 212
 213         return ret;
 214 }
 215
 216 uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state)
 217 {
 218         int32_t ret;
 219         uint64_t result;
 220
 221         /* sanity check crossover type */
 222         if (state == 0U) {
 223                 result = EINVAL;
 224         } else {
 225                 /* clean the previous response state */
 226                 ari_clobber_response(ari_base);
 227
 228                 ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_CSTATE_STATS, state, 0U);
 229                 if (ret != 0) {
 230                         result = EINVAL;
 231                 } else {
 232                         result = (uint64_t)ari_get_response_low(ari_base);
 233                 }
 234         }
 235         return result;
 236 }
 237
 238 int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats)
 239 {
 240         /* clean the previous response state */
 241         ari_clobber_response(ari_base);
 242
 243         /* write the cstate stats */
 244         return ari_request_wait(ari_base, 0U, TEGRA_ARI_WRITE_CSTATE_STATS, state,
 245                         stats);
 246 }
 247
 248 uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data)
 249 {
 250         uint64_t resp;
 251         int32_t ret;
 252         uint32_t local_data = data;
 253
 254         /* clean the previous response state */
 255         ari_clobber_response(ari_base);
 256
 257         /* ARI_REQUEST_DATA_HI is reserved for commands other than 'ECHO' */
 258         if (cmd != TEGRA_ARI_MISC_ECHO) {
 259                 local_data = 0U;
 260         }
 261
 262         ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC, cmd, local_data);
 263         if (ret != 0) {
 264                 resp = (uint64_t)ret;
 265         } else {
 266                 /* get the command response */
 267                 resp = ari_get_response_low(ari_base);
 268                 resp |= ((uint64_t)ari_get_response_high(ari_base) << 32);
 269         }
 270
 271         return resp;
 272 }
 273
 274 int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
 275 {
 276         int32_t ret;
 277         uint32_t result;
 278
 279         /* clean the previous response state */
 280         ari_clobber_response(ari_base);
 281
 282         ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7U,
 283                         wake_time);
 284         if (ret != 0) {
 285                 ERROR("%s: failed (%d)\n", __func__, ret);
 286                 result = 0U;
 287         } else {
 288                 result = ari_get_response_low(ari_base) & 0x1U;
 289         }
 290
 291         /* 1 = CCx allowed, 0 = CCx not allowed */
 292         return (int32_t)result;
 293 }
 294
 295 int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
 296 {
 297         int32_t ret, result;
 298
 299         /* check for allowed power state */
 300         if ((state != TEGRA_ARI_CORE_C0) &&
 301             (state != TEGRA_ARI_CORE_C1) &&
 302             (state != TEGRA_ARI_CORE_C6) &&
 303             (state != TEGRA_ARI_CORE_C7)) {
 304                 ERROR("%s: unknown cstate (%d)\n", __func__, state);
 305                 result = EINVAL;
 306         } else {
 307                 /* clean the previous response state */
 308                 ari_clobber_response(ari_base);
 309
 310                 ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_SC7_ALLOWED, state,
 311                                 wake_time);
 312                 if (ret != 0) {
 313                         ERROR("%s: failed (%d)\n", __func__, ret);
 314                         result = 0;
 315                 } else {
 316                         /* 1 = SC7 allowed, 0 = SC7 not allowed */
 317                         result = (ari_get_response_low(ari_base) != 0U) ? 1 : 0;
 318                 }
 319         }
 320
 321         return result;
 322 }
 323
 324 int32_t ari_online_core(uint32_t ari_base, uint32_t core)
 325 {
 326         uint64_t cpu = read_mpidr() & (uint64_t)(MPIDR_CPU_MASK);
 327         uint64_t cluster = (read_mpidr() & (uint64_t)(MPIDR_CLUSTER_MASK)) >>
 328                            (uint64_t)(MPIDR_AFFINITY_BITS);
 329         uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
 330         int32_t ret;
 331
 332         /* construct the current CPU # */
 333         cpu |= (cluster << 2);
 334
 335         /* sanity check target core id */
 336         if ((core >= MCE_CORE_ID_MAX) || (cpu == (uint64_t)core)) {
 337                 ERROR("%s: unsupported core id (%d)\n", __func__, core);
 338                 ret = EINVAL;
 339         } else {
 340                 /*
 341                  * The Denver cluster has 2 CPUs only - 0, 1.
 342                  */
 343                 if ((impl == (uint32_t)DENVER_IMPL) &&
 344                     ((core == 2U) || (core == 3U))) {
 345                         ERROR("%s: unknown core id (%d)\n", __func__, core);
 346                         ret = EINVAL;
 347                 } else {
 348                         /* clean the previous response state */
 349                         ari_clobber_response(ari_base);
 350                         ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_ONLINE_CORE, core, 0U);
 351                 }
 352         }
 353
 354         return ret;
 355 }
 356
 357 int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable)
 358 {
 359         uint32_t val;
 360
 361         /* clean the previous response state */
 362         ari_clobber_response(ari_base);
 363
 364         /*
 365          * If the enable bit is cleared, Auto-CC3 will be disabled by setting
 366          * the SW visible voltage/frequency request registers for all non
 367          * floorswept cores valid independent of StandbyWFI and disabling
 368          * the IDLE voltage/frequency request register. If set, Auto-CC3
 369          * will be enabled by setting the ARM SW visible voltage/frequency
 370          * request registers for all non floorswept cores to be enabled by
 371          * StandbyWFI or the equivalent signal, and always keeping the IDLE
 372          * voltage/frequency request register enabled.
 373          */
 374         val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\
 375                 ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
 376                 ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
 377
 378         return ari_request_wait(ari_base, 0U, TEGRA_ARI_CC3_CTRL, val, 0U);
 379 }
 380
 381 int32_t ari_reset_vector_update(uint32_t ari_base)
 382 {
 383         /* clean the previous response state */
 384         ari_clobber_response(ari_base);
 385
 386         /*
 387          * Need to program the CPU reset vector one time during cold boot
 388          * and SC7 exit
 389          */
 390         (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0U, 0U);
 391
 392         return 0;
 393 }
 394
 395 int32_t ari_roc_flush_cache_trbits(uint32_t ari_base)
 396 {
 397         /* clean the previous response state */
 398         ari_clobber_response(ari_base);
 399
 400         return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS,
 401                         0U, 0U);
 402 }
 403
 404 int32_t ari_roc_flush_cache(uint32_t ari_base)
 405 {
 406         /* clean the previous response state */
 407         ari_clobber_response(ari_base);
 408
 409         return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY,
 410                         0U, 0U);
 411 }
 412
 413 int32_t ari_roc_clean_cache(uint32_t ari_base)
 414 {
 415         /* clean the previous response state */
 416         ari_clobber_response(ari_base);
 417
 418         return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY,
 419                         0U, 0U);
 420 }
 421
 422 uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data)
 423 {
 424         uint64_t mca_arg_data, result = 0;
 425         uint32_t resp_lo, resp_hi;
 426         uint32_t mca_arg_err, mca_arg_finish;
 427         int32_t ret;
 428
 429         /* Set data (write) */
 430         mca_arg_data = (data != NULL) ? *data : 0ULL;
 431
 432         /* Set command */
 433         ari_write_32(ari_base, (uint32_t)cmd, ARI_RESPONSE_DATA_LO);
 434         ari_write_32(ari_base, (uint32_t)(cmd >> 32U), ARI_RESPONSE_DATA_HI);
 435
 436         ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MCA,
 437                                (uint32_t)mca_arg_data,
 438                                (uint32_t)(mca_arg_data >> 32U));
 439         if (ret == 0) {
 440                 resp_lo = ari_get_response_low(ari_base);
 441                 resp_hi = ari_get_response_high(ari_base);
 442
 443                 mca_arg_err = resp_lo & MCA_ARG_ERROR_MASK;
 444                 mca_arg_finish = (resp_hi >> MCA_ARG_FINISH_SHIFT) &
 445                                  MCA_ARG_FINISH_MASK;
 446
 447                 if (mca_arg_finish == 0U) {
 448                         result = (uint64_t)mca_arg_err;
 449                 } else {
 450                         if (data != NULL) {
 451                                 resp_lo = ari_get_request_low(ari_base);
 452                                 resp_hi = ari_get_request_high(ari_base);
 453                                 *data = ((uint64_t)resp_hi << 32U) |
 454                                          (uint64_t)resp_lo;
 455                         }
 456                 }
 457         }
 458
 459         return result;
 460 }
 461
 462 int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx)
 463 {
 464         int32_t ret = 0;
 465         /* sanity check GSC ID */
 466         if (gsc_idx > (uint32_t)TEGRA_ARI_GSC_VPR_IDX) {
 467                 ret = EINVAL;
 468         } else {
 469                 /* clean the previous response state */
 470                 ari_clobber_response(ari_base);
 471
 472                 /*
 473                  * The MCE code will read the GSC carveout value, corrseponding to
 474                  * the ID, from the MC registers and update the internal GSC registers
 475                  * of the CCPLEX.
 476                  */
 477                 (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0U);
 478         }
 479
 480         return ret;
 481 }
 482
 483 void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx)
 484 {
 485         /* clean the previous response state */
 486         ari_clobber_response(ari_base);
 487
 488         /*
 489          * The MCE will shutdown or restart the entire system
 490          */
 491         (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, state_idx, 0U);
 492 }
 493
 494 int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req,
 495                 uint64_t *data)
 496 {
 497         int32_t ret, result;
 498         uint32_t val;
 499         uint8_t req_cmd, req_status;
 500
 501         req_cmd = (uint8_t)(req >> UNCORE_PERFMON_CMD_SHIFT);
 502
 503         /* clean the previous response state */
 504         ari_clobber_response(ari_base);
 505
 506         /* sanity check input parameters */
 507         if ((req_cmd == UNCORE_PERFMON_CMD_READ) && (data == NULL)) {
 508                 ERROR("invalid parameters\n");
 509                 result = EINVAL;
 510         } else {
 511                 /*
 512                  * For "write" commands get the value that has to be written
 513                  * to the uncore perfmon registers
 514                  */
 515                 val = (req_cmd == UNCORE_PERFMON_CMD_WRITE) ?
 516                         (uint32_t)*data : 0U;
 517
 518                 ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_PERFMON, val,
 519                                        (uint32_t)req);
 520                 if (ret != 0) {
 521                         result = ret;
 522                 } else {
 523                         /* read the command status value */
 524                         req_status = (uint8_t)ari_get_response_high(ari_base) &
 525                                          UNCORE_PERFMON_RESP_STATUS_MASK;
 526
 527                         /*
 528                          * For "read" commands get the data from the uncore
 529                          * perfmon registers
 530                          */
 531                         req_status >>= UNCORE_PERFMON_RESP_STATUS_SHIFT;
 532                         if ((req_status == 0U) && (req_cmd == UNCORE_PERFMON_CMD_READ)) {
 533                                 *data = ari_get_response_low(ari_base);
 534                         }
 535                         result = (int32_t)req_status;
 536                 }
 537         }
 538
 539         return result;
 540 }
 541
 542 void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value)
 543 {
 544         /*
 545          * This invokes the ARI_MISC_CCPLEX commands. This can be
 546          * used to enable/disable coresight clock gating.
 547          */
 548
 549         if ((index > TEGRA_ARI_MISC_CCPLEX_EDBGREQ) ||
 550                 ((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) &&
 551                 (value > 1U))) {
 552                 ERROR("%s: invalid parameters \n", __func__);
 553         } else {
 554                 /* clean the previous response state */
 555                 ari_clobber_response(ari_base);
 556                 (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, index, value);
 557         }
 558 }