plat/qemu/qemu_bl2_setup.c

   1 /*
   2  * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6 #include <arch_helpers.h>
   7 #include <bl_common.h>
   8 #include <console.h>
   9 #include <debug.h>
  10 #include <libfdt.h>
  11 #include <platform_def.h>
  12 #include "qemu_private.h"
  13 #include <string.h>
  14 #include <utils.h>
  15
  16 /*
  17  * The next 2 constants identify the extents of the code & RO data region.
  18  * These addresses are used by the MMU setup code and therefore they must be
  19  * page-aligned.  It is the responsibility of the linker script to ensure that
  20  * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
  21  */
  22 #define BL2_RO_BASE (unsigned long)(&__RO_START__)
  23 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
  24
  25 /*******************************************************************************
  26  * This structure represents the superset of information that is passed to
  27  * BL3-1, e.g. while passing control to it from BL2, bl31_params
  28  * and other platform specific params
  29  ******************************************************************************/
  30 typedef struct bl2_to_bl31_params_mem {
  31         bl31_params_t bl31_params;
  32         image_info_t bl31_image_info;
  33         image_info_t bl32_image_info;
  34         image_info_t bl33_image_info;
  35         entry_point_info_t bl33_ep_info;
  36         entry_point_info_t bl32_ep_info;
  37         entry_point_info_t bl31_ep_info;
  38 } bl2_to_bl31_params_mem_t;
  39
  40
  41 static bl2_to_bl31_params_mem_t bl31_params_mem;
  42
  43
  44
  45 /* Data structure which holds the extents of the trusted SRAM for BL2 */
  46 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
  47
  48 meminfo_t *bl2_plat_sec_mem_layout(void)
  49 {
  50         return &bl2_tzram_layout;
  51 }
  52
  53 /*******************************************************************************
  54  * This function assigns a pointer to the memory that the platform has kept
  55  * aside to pass platform specific and trusted firmware related information
  56  * to BL31. This memory is allocated by allocating memory to
  57  * bl2_to_bl31_params_mem_t structure which is a superset of all the
  58  * structure whose information is passed to BL31
  59  * NOTE: This function should be called only once and should be done
  60  * before generating params to BL31
  61  ******************************************************************************/
  62 bl31_params_t *bl2_plat_get_bl31_params(void)
  63 {
  64         bl31_params_t *bl2_to_bl31_params;
  65
  66         /*
  67          * Initialise the memory for all the arguments that needs to
  68          * be passed to BL3-1
  69          */
  70         zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
  71
  72         /* Assign memory for TF related information */
  73         bl2_to_bl31_params = &bl31_params_mem.bl31_params;
  74         SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
  75
  76         /* Fill BL3-1 related information */
  77         bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
  78         SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
  79                 VERSION_1, 0);
  80
  81         /* Fill BL3-2 related information */
  82         bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
  83         SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
  84                 VERSION_1, 0);
  85         bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
  86         SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
  87                 VERSION_1, 0);
  88
  89         /* Fill BL3-3 related information */
  90         bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
  91         SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
  92                 PARAM_EP, VERSION_1, 0);
  93
  94         /* BL3-3 expects to receive the primary CPU MPID (through x0) */
  95         bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
  96
  97         bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
  98         SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
  99                 VERSION_1, 0);
 100
 101         return bl2_to_bl31_params;
 102 }
 103
 104 /* Flush the TF params and the TF plat params */
 105 void bl2_plat_flush_bl31_params(void)
 106 {
 107         flush_dcache_range((unsigned long)&bl31_params_mem,
 108                         sizeof(bl2_to_bl31_params_mem_t));
 109 }
 110
 111 /*******************************************************************************
 112  * This function returns a pointer to the shared memory that the platform
 113  * has kept to point to entry point information of BL31 to BL2
 114  ******************************************************************************/
 115 struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
 116 {
 117 #if DEBUG
 118         bl31_params_mem.bl31_ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL;
 119 #endif
 120
 121         return &bl31_params_mem.bl31_ep_info;
 122 }
 123
 124
 125
 126 void bl2_early_platform_setup(meminfo_t *mem_layout)
 127 {
 128         /* Initialize the console to provide early debug support */
 129         console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
 130                         PLAT_QEMU_CONSOLE_BAUDRATE);
 131
 132         /* Setup the BL2 memory layout */
 133         bl2_tzram_layout = *mem_layout;
 134
 135         plat_qemu_io_setup();
 136 }
 137
 138 static void security_setup(void)
 139 {
 140         /*
 141          * This is where a TrustZone address space controller and other
 142          * security related peripherals, would be configured.
 143          */
 144 }
 145
 146 static void update_dt(void)
 147 {
 148         int ret;
 149         void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE;
 150
 151         ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
 152         if (ret < 0) {
 153                 ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
 154                 return;
 155         }
 156
 157         if (dt_add_psci_node(fdt)) {
 158                 ERROR("Failed to add PSCI Device Tree node\n");
 159                 return;
 160         }
 161
 162         if (dt_add_psci_cpu_enable_methods(fdt)) {
 163                 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
 164                 return;
 165         }
 166
 167         ret = fdt_pack(fdt);
 168         if (ret < 0)
 169                 ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
 170 }
 171
 172 void bl2_platform_setup(void)
 173 {
 174         security_setup();
 175         update_dt();
 176
 177         /* TODO Initialize timer */
 178 }
 179
 180 void bl2_plat_arch_setup(void)
 181 {
 182         qemu_configure_mmu_el1(bl2_tzram_layout.total_base,
 183                               bl2_tzram_layout.total_size,
 184                               BL2_RO_BASE, BL2_RO_LIMIT,
 185                               BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
 186 }
 187
 188 /*******************************************************************************
 189  * Gets SPSR for BL32 entry
 190  ******************************************************************************/
 191 static uint32_t qemu_get_spsr_for_bl32_entry(void)
 192 {
 193         /*
 194          * The Secure Payload Dispatcher service is responsible for
 195          * setting the SPSR prior to entry into the BL3-2 image.
 196          */
 197         return 0;
 198 }
 199
 200 /*******************************************************************************
 201  * Gets SPSR for BL33 entry
 202  ******************************************************************************/
 203 static uint32_t qemu_get_spsr_for_bl33_entry(void)
 204 {
 205         unsigned int mode;
 206         uint32_t spsr;
 207
 208         /* Figure out what mode we enter the non-secure world in */
 209         mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
 210
 211         /*
 212          * TODO: Consider the possibility of specifying the SPSR in
 213          * the FIP ToC and allowing the platform to have a say as
 214          * well.
 215          */
 216         spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
 217         return spsr;
 218 }
 219
 220 /*******************************************************************************
 221  * Before calling this function BL3-1 is loaded in memory and its entrypoint
 222  * is set by load_image. This is a placeholder for the platform to change
 223  * the entrypoint of BL3-1 and set SPSR and security state.
 224  * On ARM standard platforms we only set the security state of the entrypoint
 225  ******************************************************************************/
 226 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
 227                                         entry_point_info_t *bl31_ep_info)
 228 {
 229         SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
 230         bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
 231                                         DISABLE_ALL_EXCEPTIONS);
 232 }
 233
 234 /*******************************************************************************
 235  * Before calling this function BL3-2 is loaded in memory and its entrypoint
 236  * is set by load_image. This is a placeholder for the platform to change
 237  * the entrypoint of BL3-2 and set SPSR and security state.
 238  * On ARM standard platforms we only set the security state of the entrypoint
 239  ******************************************************************************/
 240 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
 241                                         entry_point_info_t *bl32_ep_info)
 242 {
 243         SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
 244         bl32_ep_info->spsr = qemu_get_spsr_for_bl32_entry();
 245 }
 246
 247 /*******************************************************************************
 248  * Before calling this function BL3-3 is loaded in memory and its entrypoint
 249  * is set by load_image. This is a placeholder for the platform to change
 250  * the entrypoint of BL3-3 and set SPSR and security state.
 251  * On ARM standard platforms we only set the security state of the entrypoint
 252  ******************************************************************************/
 253 void bl2_plat_set_bl33_ep_info(image_info_t *image,
 254                                         entry_point_info_t *bl33_ep_info)
 255 {
 256
 257         SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
 258         bl33_ep_info->spsr = qemu_get_spsr_for_bl33_entry();
 259 }
 260
 261 /*******************************************************************************
 262  * Populate the extents of memory available for loading BL32
 263  ******************************************************************************/
 264 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
 265 {
 266         /*
 267          * Populate the extents of memory available for loading BL32.
 268          */
 269         bl32_meminfo->total_base = BL32_BASE;
 270         bl32_meminfo->free_base = BL32_BASE;
 271         bl32_meminfo->total_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
 272         bl32_meminfo->free_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
 273 }
 274
 275 /*******************************************************************************
 276  * Populate the extents of memory available for loading BL33
 277  ******************************************************************************/
 278 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
 279 {
 280         bl33_meminfo->total_base = NS_DRAM0_BASE;
 281         bl33_meminfo->total_size = NS_DRAM0_SIZE;
 282         bl33_meminfo->free_base = NS_DRAM0_BASE;
 283         bl33_meminfo->free_size = NS_DRAM0_SIZE;
 284 }
 285
 286 unsigned long plat_get_ns_image_entrypoint(void)
 287 {
 288         return NS_IMAGE_OFFSET;
 289 }