plat/qemu/qemu_bl2_setup.c

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6 #include <arch_helpers.h>
   7 #include <assert.h>
   8 #include <bl_common.h>
   9 #include <debug.h>
  10 #include <desc_image_load.h>
  11 #include <optee_utils.h>
  12 #include <libfdt.h>
  13 #include <platform.h>
  14 #include <platform_def.h>
  15 #include <string.h>
  16 #include <utils.h>
  17 #include "qemu_private.h"
  18
  19
  20 /* Data structure which holds the extents of the trusted SRAM for BL2 */
  21 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
  22
  23 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
  24                                u_register_t arg2, u_register_t arg3)
  25 {
  26         meminfo_t *mem_layout = (void *)arg1;
  27
  28         /* Initialize the console to provide early debug support */
  29         qemu_console_init();
  30
  31         /* Setup the BL2 memory layout */
  32         bl2_tzram_layout = *mem_layout;
  33
  34         plat_qemu_io_setup();
  35 }
  36
  37 static void security_setup(void)
  38 {
  39         /*
  40          * This is where a TrustZone address space controller and other
  41          * security related peripherals, would be configured.
  42          */
  43 }
  44
  45 static void update_dt(void)
  46 {
  47         int ret;
  48         void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE;
  49
  50         ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
  51         if (ret < 0) {
  52                 ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
  53                 return;
  54         }
  55
  56         if (dt_add_psci_node(fdt)) {
  57                 ERROR("Failed to add PSCI Device Tree node\n");
  58                 return;
  59         }
  60
  61         if (dt_add_psci_cpu_enable_methods(fdt)) {
  62                 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
  63                 return;
  64         }
  65
  66         ret = fdt_pack(fdt);
  67         if (ret < 0)
  68                 ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
  69 }
  70
  71 void bl2_platform_setup(void)
  72 {
  73         security_setup();
  74         update_dt();
  75
  76         /* TODO Initialize timer */
  77 }
  78
  79 #ifdef AARCH32
  80 #define QEMU_CONFIGURE_BL2_MMU(...)     qemu_configure_mmu_svc_mon(__VA_ARGS__)
  81 #else
  82 #define QEMU_CONFIGURE_BL2_MMU(...)     qemu_configure_mmu_el1(__VA_ARGS__)
  83 #endif
  84
  85 void bl2_plat_arch_setup(void)
  86 {
  87         QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base,
  88                               bl2_tzram_layout.total_size,
  89                               BL_CODE_BASE, BL_CODE_END,
  90                               BL_RO_DATA_BASE, BL_RO_DATA_END,
  91                               BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
  92 }
  93
  94 /*******************************************************************************
  95  * Gets SPSR for BL32 entry
  96  ******************************************************************************/
  97 static uint32_t qemu_get_spsr_for_bl32_entry(void)
  98 {
  99 #ifdef AARCH64
 100         /*
 101          * The Secure Payload Dispatcher service is responsible for
 102          * setting the SPSR prior to entry into the BL3-2 image.
 103          */
 104         return 0;
 105 #else
 106         return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
 107                            DISABLE_ALL_EXCEPTIONS);
 108 #endif
 109 }
 110
 111 /*******************************************************************************
 112  * Gets SPSR for BL33 entry
 113  ******************************************************************************/
 114 static uint32_t qemu_get_spsr_for_bl33_entry(void)
 115 {
 116         uint32_t spsr;
 117 #ifdef AARCH64
 118         unsigned int mode;
 119
 120         /* Figure out what mode we enter the non-secure world in */
 121         mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
 122
 123         /*
 124          * TODO: Consider the possibility of specifying the SPSR in
 125          * the FIP ToC and allowing the platform to have a say as
 126          * well.
 127          */
 128         spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
 129 #else
 130         spsr = SPSR_MODE32(MODE32_svc,
 131                     plat_get_ns_image_entrypoint() & 0x1,
 132                     SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 133 #endif
 134         return spsr;
 135 }
 136
 137 static int qemu_bl2_handle_post_image_load(unsigned int image_id)
 138 {
 139         int err = 0;
 140         bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
 141 #if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
 142         bl_mem_params_node_t *pager_mem_params = NULL;
 143         bl_mem_params_node_t *paged_mem_params = NULL;
 144 #endif
 145
 146         assert(bl_mem_params);
 147
 148         switch (image_id) {
 149         case BL32_IMAGE_ID:
 150 #if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
 151                 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
 152                 assert(pager_mem_params);
 153
 154                 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
 155                 assert(paged_mem_params);
 156
 157                 err = parse_optee_header(&bl_mem_params->ep_info,
 158                                          &pager_mem_params->image_info,
 159                                          &paged_mem_params->image_info);
 160                 if (err != 0) {
 161                         WARN("OPTEE header parse error.\n");
 162                 }
 163
 164 #if defined(SPD_opteed)
 165                 /*
 166                  * OP-TEE expect to receive DTB address in x2.
 167                  * This will be copied into x2 by dispatcher.
 168                  */
 169                 bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE;
 170 #else /* case AARCH32_SP_OPTEE */
 171                 bl_mem_params->ep_info.args.arg0 =
 172                                         bl_mem_params->ep_info.args.arg1;
 173                 bl_mem_params->ep_info.args.arg1 = 0;
 174                 bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE;
 175                 bl_mem_params->ep_info.args.arg3 = 0;
 176 #endif
 177 #endif
 178                 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
 179                 break;
 180
 181         case BL33_IMAGE_ID:
 182 #ifdef AARCH32_SP_OPTEE
 183                 /* AArch32 only core: OP-TEE expects NSec EP in register LR */
 184                 pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
 185                 assert(pager_mem_params);
 186                 pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
 187 #endif
 188
 189                 /* BL33 expects to receive the primary CPU MPID (through r0) */
 190                 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
 191                 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
 192                 break;
 193         default:
 194                 /* Do nothing in default case */
 195                 break;
 196         }
 197
 198         return err;
 199 }
 200
 201 /*******************************************************************************
 202  * This function can be used by the platforms to update/use image
 203  * information for given `image_id`.
 204  ******************************************************************************/
 205 int bl2_plat_handle_post_image_load(unsigned int image_id)
 206 {
 207         return qemu_bl2_handle_post_image_load(image_id);
 208 }
 209
 210 uintptr_t plat_get_ns_image_entrypoint(void)
 211 {
 212         return NS_IMAGE_OFFSET;
 213 }