2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
7 #include <arch_helpers.h>
12 #include <gic_common.h>
16 #include <platform_def.h>
18 #include <xlat_tables.h>
19 #include "../qemu_private.h"
22 #error qemu does not support RESET_TO_SP_MIN
25 static entry_point_info_t bl33_image_ep_info
;
28 * The next 3 constants identify the extents of the code, RO data region and the
29 * limit of the BL3-1 image. These addresses are used by the MMU setup code and
30 * therefore they must be page-aligned. It is the responsibility of the linker
31 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
32 * refer to page-aligned addresses.
34 #define BL32_RO_BASE (unsigned long)(&__RO_START__)
35 #define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
36 #define BL32_END (unsigned long)(&__BL32_END__)
40 * The next 2 constants identify the extents of the coherent memory region.
41 * These addresses are used by the MMU setup code and therefore they must be
42 * page-aligned. It is the responsibility of the linker script to ensure that
43 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
44 * refer to page-aligned addresses.
46 #define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
47 #define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
50 /******************************************************************************
51 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
53 *****************************************************************************/
54 #define PLATFORM_G1S_PROPS(grp) \
55 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
56 grp, GIC_INTR_CFG_LEVEL), \
57 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
58 grp, GIC_INTR_CFG_LEVEL), \
59 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
60 grp, GIC_INTR_CFG_LEVEL), \
61 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
62 grp, GIC_INTR_CFG_LEVEL), \
63 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
64 grp, GIC_INTR_CFG_LEVEL), \
65 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
66 grp, GIC_INTR_CFG_LEVEL), \
67 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
68 grp, GIC_INTR_CFG_LEVEL), \
69 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
70 grp, GIC_INTR_CFG_LEVEL)
72 #define PLATFORM_G0_PROPS(grp)
74 static const interrupt_prop_t stih410_interrupt_props
[] = {
75 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0
),
76 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0
)
79 static unsigned int target_mask_array
[PLATFORM_CORE_COUNT
];
81 static const struct gicv2_driver_data plat_gicv2_driver_data
= {
82 .gicd_base
= GICD_BASE
,
83 .gicc_base
= GICC_BASE
,
84 .interrupt_props
= stih410_interrupt_props
,
85 .interrupt_props_num
= ARRAY_SIZE(stih410_interrupt_props
),
86 .target_masks
= target_mask_array
,
87 .target_masks_num
= ARRAY_SIZE(target_mask_array
),
90 /*******************************************************************************
91 * Return a pointer to the 'entry_point_info' structure of the next image for
92 * the security state specified. BL33 corresponds to the non-secure image type
93 * while BL32 corresponds to the secure image type. A NULL pointer is returned
94 * if the image does not exist.
95 ******************************************************************************/
96 entry_point_info_t
*sp_min_plat_get_bl33_ep_info(void)
98 entry_point_info_t
*next_image_info
= &bl33_image_ep_info
;
101 * None of the images on the ARM development platforms can have 0x0
104 if (next_image_info
->pc
)
105 return next_image_info
;
110 void sp_min_early_platform_setup2(u_register_t arg0
, u_register_t arg1
,
111 u_register_t arg2
, u_register_t arg3
)
113 bl_params_t
*params_from_bl2
= (bl_params_t
*)arg0
;
115 /* Initialize the console to provide early debug support */
116 console_init(PLAT_QEMU_BOOT_UART_BASE
, PLAT_QEMU_BOOT_UART_CLK_IN_HZ
,
117 PLAT_QEMU_CONSOLE_BAUDRATE
);
119 ERROR("qemu sp_min, console init\n");
121 * Check params passed from BL2
123 assert(params_from_bl2
);
124 assert(params_from_bl2
->h
.type
== PARAM_BL_PARAMS
);
125 assert(params_from_bl2
->h
.version
>= VERSION_2
);
127 bl_params_node_t
*bl_params
= params_from_bl2
->head
;
130 * Copy BL33 entry point information from BL2's address space.
133 if (bl_params
->image_id
== BL33_IMAGE_ID
)
134 bl33_image_ep_info
= *bl_params
->ep_info
;
136 bl_params
= bl_params
->next_params_info
;
139 if (!bl33_image_ep_info
.pc
)
143 void sp_min_plat_arch_setup(void)
145 qemu_configure_mmu_svc_mon(BL32_RO_BASE
, BL32_END
- BL32_RO_BASE
,
146 BL32_RO_BASE
, BL32_RO_LIMIT
,
147 BL_COHERENT_RAM_BASE
, BL_COHERENT_RAM_END
);
151 void sp_min_platform_setup(void)
153 /* Initialize the gic cpu and distributor interfaces */
154 gicv2_driver_init(&plat_gicv2_driver_data
);
156 gicv2_pcpu_distif_init();
157 gicv2_cpuif_enable();
160 unsigned int plat_get_syscnt_freq2(void)
162 return SYS_COUNTER_FREQ_IN_TICKS
;
165 void sp_min_plat_fiq_handler(uint32_t id
)
167 VERBOSE("[sp_min] interrupt #%d\n", id
);