plat/renesas/rcar/bl2_plat_setup.c

   1 /*
   2  * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <string.h>
   8
   9 #include <libfdt.h>
  10
  11 #include <platform_def.h>
  12
  13 #include <arch_helpers.h>
  14 #include <bl1/bl1.h>
  15 #include <common/bl_common.h>
  16 #include <common/debug.h>
  17 #include <common/desc_image_load.h>
  18 #include <drivers/console.h>
  19 #include <lib/mmio.h>
  20 #include <lib/xlat_tables/xlat_tables_defs.h>
  21 #include <plat/common/platform.h>
  22
  23 #include "avs_driver.h"
  24 #include "boot_init_dram.h"
  25 #include "cpg_registers.h"
  26 #include "board.h"
  27 #include "emmc_def.h"
  28 #include "emmc_hal.h"
  29 #include "emmc_std.h"
  30
  31 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
  32 #include "iic_dvfs.h"
  33 #endif
  34
  35 #include "io_common.h"
  36 #include "qos_init.h"
  37 #include "rcar_def.h"
  38 #include "rcar_private.h"
  39 #include "rcar_version.h"
  40 #include "rom_api.h"
  41
  42 IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE)
  43 IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT)
  44
  45 #if USE_COHERENT_MEM
  46 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE)
  47 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT)
  48 #endif
  49
  50 extern void plat_rcar_gic_driver_init(void);
  51 extern void plat_rcar_gic_init(void);
  52 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
  53 extern void bl2_system_cpg_init(void);
  54 extern void bl2_secure_setting(void);
  55 extern void bl2_cpg_init(void);
  56 extern void rcar_io_emmc_setup(void);
  57 extern void rcar_io_setup(void);
  58 extern void rcar_swdt_release(void);
  59 extern void rcar_swdt_init(void);
  60 extern void rcar_rpc_init(void);
  61 extern void rcar_pfc_init(void);
  62 extern void rcar_dma_init(void);
  63
  64 /* R-Car Gen3 product check */
  65 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
  66 #define TARGET_PRODUCT                  RCAR_PRODUCT_H3
  67 #define TARGET_NAME                     "R-Car H3"
  68 #elif RCAR_LSI == RCAR_M3
  69 #define TARGET_PRODUCT                  RCAR_PRODUCT_M3
  70 #define TARGET_NAME                     "R-Car M3"
  71 #elif RCAR_LSI == RCAR_M3N
  72 #define TARGET_PRODUCT                  RCAR_PRODUCT_M3N
  73 #define TARGET_NAME                     "R-Car M3N"
  74 #elif RCAR_LSI == RCAR_E3
  75 #define TARGET_PRODUCT                  RCAR_PRODUCT_E3
  76 #define TARGET_NAME                     "R-Car E3"
  77 #endif
  78
  79 #if (RCAR_LSI == RCAR_E3)
  80 #define GPIO_INDT                       (GPIO_INDT6)
  81 #define GPIO_BKUP_TRG_SHIFT             ((uint32_t)1U<<13U)
  82 #else
  83 #define GPIO_INDT                       (GPIO_INDT1)
  84 #define GPIO_BKUP_TRG_SHIFT             ((uint32_t)1U<<8U)
  85 #endif
  86
  87 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
  88          < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
  89         assert_bl31_params_do_not_fit_in_shared_memory);
  90
  91 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
  92
  93 /* FDT with DRAM configuration */
  94 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)];
  95 static void *fdt = (void *)fdt_blob;
  96
  97 static void unsigned_num_print(unsigned long long int unum, unsigned int radix,
  98                                 char *string)
  99 {
 100         /* Just need enough space to store 64 bit decimal integer */
 101         char num_buf[20];
 102         int i = 0;
 103         unsigned int rem;
 104
 105         do {
 106                 rem = unum % radix;
 107                 if (rem < 0xa)
 108                         num_buf[i] = '0' + rem;
 109                 else
 110                         num_buf[i] = 'a' + (rem - 0xa);
 111                 i++;
 112                 unum /= radix;
 113         } while (unum > 0U);
 114
 115         while (--i >= 0)
 116                 *string++ = num_buf[i];
 117 }
 118
 119 #if (RCAR_LOSSY_ENABLE == 1)
 120 typedef struct bl2_lossy_info {
 121         uint32_t magic;
 122         uint32_t a0;
 123         uint32_t b0;
 124 } bl2_lossy_info_t;
 125
 126 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr,
 127                               uint64_t end_addr, uint32_t format,
 128                               uint32_t enable, int fcnlnode)
 129 {
 130         const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr);
 131         char nodename[40] = { 0 };
 132         int ret, node;
 133
 134         /* Ignore undefined addresses */
 135         if (start_addr == 0 && end_addr == 0)
 136                 return;
 137
 138         snprintf(nodename, sizeof(nodename), "lossy-decompression@");
 139         unsigned_num_print(start_addr, 16, nodename + strlen(nodename));
 140
 141         node = ret = fdt_add_subnode(fdt, fcnlnode, nodename);
 142         if (ret < 0) {
 143                 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret);
 144                 panic();
 145         }
 146
 147         ret = fdt_setprop_string(fdt, node, "compatible",
 148                                  "renesas,lossy-decompression");
 149         if (ret < 0) {
 150                 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret);
 151                 panic();
 152         }
 153
 154         ret = fdt_appendprop_string(fdt, node, "compatible",
 155                                     "shared-dma-pool");
 156         if (ret < 0) {
 157                 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret);
 158                 panic();
 159         }
 160
 161         ret = fdt_setprop_u64(fdt, node, "reg", start_addr);
 162         if (ret < 0) {
 163                 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret);
 164                 panic();
 165         }
 166
 167         ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize));
 168         if (ret < 0) {
 169                 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret);
 170                 panic();
 171         }
 172
 173         ret = fdt_setprop(fdt, node, "no-map", NULL, 0);
 174         if (ret < 0) {
 175                 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret);
 176                 panic();
 177         }
 178
 179         ret = fdt_setprop_u32(fdt, node, "renesas,formats", format);
 180         if (ret < 0) {
 181                 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret);
 182                 panic();
 183         }
 184 }
 185
 186 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr,
 187                               uint64_t end_addr, uint32_t format,
 188                               uint32_t enable, int fcnlnode)
 189 {
 190         bl2_lossy_info_t info;
 191         uint32_t reg;
 192
 193         bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode);
 194
 195         reg = format | (start_addr >> 20);
 196         mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg);
 197         mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20);
 198         mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable);
 199
 200         info.magic = 0x12345678U;
 201         info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no);
 202         info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no);
 203
 204         mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic);
 205         mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0);
 206         mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0);
 207
 208         NOTICE("     Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no,
 209                mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no),
 210                mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no));
 211 }
 212 #endif
 213
 214 void bl2_plat_flush_bl31_params(void)
 215 {
 216         uint32_t product_cut, product, cut;
 217         uint32_t boot_dev, boot_cpu;
 218         uint32_t lcs, reg, val;
 219
 220         reg = mmio_read_32(RCAR_MODEMR);
 221         boot_dev = reg & MODEMR_BOOT_DEV_MASK;
 222
 223         if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
 224             boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
 225                 emmc_terminate();
 226
 227         if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7)
 228                 bl2_secure_setting();
 229
 230         reg = mmio_read_32(RCAR_PRR);
 231         product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
 232         product = reg & RCAR_PRODUCT_MASK;
 233         cut = reg & RCAR_CUT_MASK;
 234
 235         if (product == RCAR_PRODUCT_M3)
 236                 goto tlb;
 237
 238         if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut)
 239                 goto tlb;
 240
 241         /* Disable MFIS write protection */
 242         mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1);
 243
 244 tlb:
 245         reg = mmio_read_32(RCAR_MODEMR);
 246         boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
 247         if (boot_cpu != MODEMR_BOOT_CPU_CA57 &&
 248             boot_cpu != MODEMR_BOOT_CPU_CA53)
 249                 goto mmu;
 250
 251         if (product_cut == RCAR_PRODUCT_H3_CUT20) {
 252                 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
 253                 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
 254                 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
 255                 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
 256                 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
 257                 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
 258         } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) ||
 259                    product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) {
 260                 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
 261                 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
 262         } else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
 263                 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
 264                 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
 265         }
 266
 267         if (product_cut == (RCAR_PRODUCT_H3_CUT20) ||
 268             product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) ||
 269             product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) ||
 270             product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
 271                 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
 272                 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
 273                 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
 274
 275                 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE);
 276                 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE);
 277         }
 278
 279 mmu:
 280         mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE);
 281         mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT);
 282
 283         val = rcar_rom_get_lcs(&lcs);
 284         if (val) {
 285                 ERROR("BL2: Failed to get the LCS. (%d)\n", val);
 286                 panic();
 287         }
 288
 289         if (lcs == LCS_SE)
 290                 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT);
 291
 292         rcar_swdt_release();
 293         bl2_system_cpg_init();
 294
 295 #if RCAR_BL2_DCACHE == 1
 296         /* Disable data cache (clean and invalidate) */
 297         disable_mmu_el3();
 298 #endif
 299 }
 300
 301 static uint32_t is_ddr_backup_mode(void)
 302 {
 303 #if RCAR_SYSTEM_SUSPEND
 304         static uint32_t reason = RCAR_COLD_BOOT;
 305         static uint32_t once;
 306
 307 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
 308         uint8_t data;
 309 #endif
 310         if (once)
 311                 return reason;
 312
 313         once = 1;
 314         if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0)
 315                 return reason;
 316
 317 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
 318         if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) {
 319                 ERROR("BL2: REG Keep10 READ ERROR.\n");
 320                 panic();
 321         }
 322
 323         if (KEEP10_MAGIC != data)
 324                 reason = RCAR_WARM_BOOT;
 325 #else
 326         reason = RCAR_WARM_BOOT;
 327 #endif
 328         return reason;
 329 #else
 330         return RCAR_COLD_BOOT;
 331 #endif
 332 }
 333
 334 int bl2_plat_handle_pre_image_load(unsigned int image_id)
 335 {
 336         u_register_t *boot_kind = (void *) BOOT_KIND_BASE;
 337         bl_mem_params_node_t *bl_mem_params;
 338
 339         if (image_id != BL31_IMAGE_ID)
 340                 return 0;
 341
 342         bl_mem_params = get_bl_mem_params_node(image_id);
 343
 344         if (is_ddr_backup_mode() == RCAR_COLD_BOOT)
 345                 goto cold_boot;
 346
 347         *boot_kind  = RCAR_WARM_BOOT;
 348         flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
 349
 350         console_flush();
 351         bl2_plat_flush_bl31_params();
 352
 353         /* will not return */
 354         bl2_enter_bl31(&bl_mem_params->ep_info);
 355
 356 cold_boot:
 357         *boot_kind  = RCAR_COLD_BOOT;
 358         flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
 359
 360         return 0;
 361 }
 362
 363 int bl2_plat_handle_post_image_load(unsigned int image_id)
 364 {
 365         static bl2_to_bl31_params_mem_t *params;
 366         bl_mem_params_node_t *bl_mem_params;
 367
 368         if (!params) {
 369                 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE;
 370                 memset((void *)PARAMS_BASE, 0, sizeof(*params));
 371         }
 372
 373         bl_mem_params = get_bl_mem_params_node(image_id);
 374
 375         switch (image_id) {
 376         case BL31_IMAGE_ID:
 377                 break;
 378         case BL32_IMAGE_ID:
 379                 memcpy(&params->bl32_ep_info, &bl_mem_params->ep_info,
 380                         sizeof(entry_point_info_t));
 381                 break;
 382         case BL33_IMAGE_ID:
 383                 memcpy(&params->bl33_ep_info, &bl_mem_params->ep_info,
 384                         sizeof(entry_point_info_t));
 385                 break;
 386         }
 387
 388         return 0;
 389 }
 390
 391 meminfo_t *bl2_plat_sec_mem_layout(void)
 392 {
 393         return &bl2_tzram_layout;
 394 }
 395
 396 static void bl2_populate_compatible_string(void *fdt)
 397 {
 398         uint32_t board_type;
 399         uint32_t board_rev;
 400         uint32_t reg;
 401         int ret;
 402
 403         /* Populate compatible string */
 404         rcar_get_board_type(&board_type, &board_rev);
 405         switch (board_type) {
 406         case BOARD_SALVATOR_X:
 407                 ret = fdt_setprop_string(fdt, 0, "compatible",
 408                                          "renesas,salvator-x");
 409                 break;
 410         case BOARD_SALVATOR_XS:
 411                 ret = fdt_setprop_string(fdt, 0, "compatible",
 412                                          "renesas,salvator-xs");
 413                 break;
 414         case BOARD_STARTER_KIT:
 415                 ret = fdt_setprop_string(fdt, 0, "compatible",
 416                                          "renesas,m3ulcb");
 417                 break;
 418         case BOARD_STARTER_KIT_PRE:
 419                 ret = fdt_setprop_string(fdt, 0, "compatible",
 420                                          "renesas,h3ulcb");
 421                 break;
 422         case BOARD_EBISU:
 423         case BOARD_EBISU_4D:
 424                 ret = fdt_setprop_string(fdt, 0, "compatible",
 425                                          "renesas,ebisu");
 426                 break;
 427         default:
 428                 NOTICE("BL2: Cannot set compatible string, board unsupported\n");
 429                 panic();
 430         }
 431
 432         if (ret < 0) {
 433                 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
 434                 panic();
 435         }
 436
 437         reg = mmio_read_32(RCAR_PRR);
 438         switch (reg & RCAR_PRODUCT_MASK) {
 439         case RCAR_PRODUCT_H3:
 440                 ret = fdt_appendprop_string(fdt, 0, "compatible",
 441                                             "renesas,r8a7795");
 442                 break;
 443         case RCAR_PRODUCT_M3:
 444                 ret = fdt_appendprop_string(fdt, 0, "compatible",
 445                                             "renesas,r8a7796");
 446                 break;
 447         case RCAR_PRODUCT_M3N:
 448                 ret = fdt_appendprop_string(fdt, 0, "compatible",
 449                                             "renesas,r8a77965");
 450                 break;
 451         case RCAR_PRODUCT_E3:
 452                 ret = fdt_appendprop_string(fdt, 0, "compatible",
 453                                             "renesas,r8a77990");
 454                 break;
 455         default:
 456                 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
 457                 panic();
 458         }
 459
 460         if (ret < 0) {
 461                 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
 462                 panic();
 463         }
 464 }
 465
 466 static void bl2_advertise_dram_entries(uint64_t dram_config[8])
 467 {
 468         char nodename[32] = { 0 };
 469         uint64_t start, size;
 470         uint64_t fdtsize;
 471         int ret, node, chan;
 472
 473         for (chan = 0; chan < 4; chan++) {
 474                 start = dram_config[2 * chan];
 475                 size = dram_config[2 * chan + 1];
 476                 if (!size)
 477                         continue;
 478
 479                 NOTICE("BL2: CH%d: %llx - %llx, %lld GiB\n",
 480                         chan, start, start + size - 1, size >> 30);
 481         }
 482
 483         /*
 484          * We add the DT nodes in reverse order here. The fdt_add_subnode()
 485          * adds the DT node before the first existing DT node, so we have
 486          * to add them in reverse order to get nodes sorted by address in
 487          * the resulting DT.
 488          */
 489         for (chan = 3; chan >= 0; chan--) {
 490                 start = dram_config[2 * chan];
 491                 size = dram_config[2 * chan + 1];
 492                 if (!size)
 493                         continue;
 494
 495                 /*
 496                  * Channel 0 is mapped in 32bit space and the first
 497                  * 128 MiB are reserved
 498                  */
 499                 if (chan == 0) {
 500                         start = 0x48000000;
 501                         size -= 0x8000000;
 502                 }
 503
 504                 fdtsize = cpu_to_fdt64(size);
 505
 506                 snprintf(nodename, sizeof(nodename), "memory@");
 507                 unsigned_num_print(start, 16, nodename + strlen(nodename));
 508                 node = ret = fdt_add_subnode(fdt, 0, nodename);
 509                 if (ret < 0)
 510                         goto err;
 511
 512                 ret = fdt_setprop_string(fdt, node, "device_type", "memory");
 513                 if (ret < 0)
 514                         goto err;
 515
 516                 ret = fdt_setprop_u64(fdt, node, "reg", start);
 517                 if (ret < 0)
 518                         goto err;
 519
 520                 ret = fdt_appendprop(fdt, node, "reg", &fdtsize,
 521                                      sizeof(fdtsize));
 522                 if (ret < 0)
 523                         goto err;
 524         }
 525
 526         return;
 527 err:
 528         NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret);
 529         panic();
 530 }
 531
 532 static void bl2_advertise_dram_size(uint32_t product)
 533 {
 534         uint64_t dram_config[8] = {
 535                 [0] = 0x400000000ULL,
 536                 [2] = 0x500000000ULL,
 537                 [4] = 0x600000000ULL,
 538                 [6] = 0x700000000ULL,
 539         };
 540
 541         switch (product) {
 542         case RCAR_PRODUCT_H3:
 543 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
 544                 /* 4GB(1GBx4) */
 545                 dram_config[1] = 0x40000000ULL;
 546                 dram_config[3] = 0x40000000ULL;
 547                 dram_config[5] = 0x40000000ULL;
 548                 dram_config[7] = 0x40000000ULL;
 549 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \
 550       (RCAR_DRAM_CHANNEL        == 5) && \
 551       (RCAR_DRAM_SPLIT          == 2)
 552                 /* 4GB(2GBx2 2ch split) */
 553                 dram_config[1] = 0x80000000ULL;
 554                 dram_config[3] = 0x80000000ULL;
 555 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
 556                 /* 8GB(2GBx4: default) */
 557                 dram_config[1] = 0x80000000ULL;
 558                 dram_config[3] = 0x80000000ULL;
 559                 dram_config[5] = 0x80000000ULL;
 560                 dram_config[7] = 0x80000000ULL;
 561 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
 562                 break;
 563
 564         case RCAR_PRODUCT_M3:
 565                 /* 4GB(2GBx2 2ch split) */
 566                 dram_config[1] = 0x80000000ULL;
 567                 dram_config[5] = 0x80000000ULL;
 568                 break;
 569
 570         case RCAR_PRODUCT_M3N:
 571                 /* 2GB(1GBx2) */
 572                 dram_config[1] = 0x80000000ULL;
 573                 break;
 574
 575         case RCAR_PRODUCT_E3:
 576 #if (RCAR_DRAM_DDR3L_MEMCONF == 0)
 577                 /* 1GB(512MBx2) */
 578                 dram_config[1] = 0x40000000ULL;
 579 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
 580                 /* 2GB(512MBx4) */
 581                 dram_config[1] = 0x80000000ULL;
 582 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
 583                 /* 4GB(1GBx4) */
 584                 dram_config[1] = 0x100000000ULL;
 585 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
 586                 break;
 587         }
 588
 589         bl2_advertise_dram_entries(dram_config);
 590 }
 591
 592 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
 593                                   u_register_t arg3, u_register_t arg4)
 594 {
 595         uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev;
 596         uint32_t product, product_cut, major, minor;
 597         int32_t ret;
 598         const char *str;
 599         const char *unknown = "unknown";
 600         const char *cpu_ca57 = "CA57";
 601         const char *cpu_ca53 = "CA53";
 602         const char *product_m3n = "M3N";
 603         const char *product_h3 = "H3";
 604         const char *product_m3 = "M3";
 605         const char *product_e3 = "E3";
 606         const char *lcs_secure = "SE";
 607         const char *lcs_cm = "CM";
 608         const char *lcs_dm = "DM";
 609         const char *lcs_sd = "SD";
 610         const char *lcs_fa = "FA";
 611         const char *sscg_off = "PLL1 nonSSCG Clock select";
 612         const char *sscg_on = "PLL1 SSCG Clock select";
 613         const char *boot_hyper80 = "HyperFlash(80MHz)";
 614         const char *boot_qspi40 = "QSPI Flash(40MHz)";
 615         const char *boot_qspi80 = "QSPI Flash(80MHz)";
 616         const char *boot_emmc25x1 = "eMMC(25MHz x1)";
 617         const char *boot_emmc50x8 = "eMMC(50MHz x8)";
 618 #if RCAR_LSI == RCAR_E3
 619         const char *boot_hyper160 = "HyperFlash(150MHz)";
 620 #else
 621         const char *boot_hyper160 = "HyperFlash(160MHz)";
 622 #endif
 623 #if (RCAR_LOSSY_ENABLE == 1)
 624         int fcnlnode;
 625 #endif
 626
 627         reg = mmio_read_32(RCAR_MODEMR);
 628         boot_dev = reg & MODEMR_BOOT_DEV_MASK;
 629         boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
 630
 631         bl2_cpg_init();
 632
 633         if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
 634             boot_cpu == MODEMR_BOOT_CPU_CA53) {
 635                 rcar_pfc_init();
 636                 /* console configuration (platform specific) done in driver */
 637                 console_init(0, 0, 0);
 638         }
 639
 640         plat_rcar_gic_driver_init();
 641         plat_rcar_gic_init();
 642         rcar_swdt_init();
 643
 644         /* FIQ interrupts are taken to EL3 */
 645         write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
 646
 647         write_daifclr(DAIF_FIQ_BIT);
 648
 649         reg = read_midr();
 650         midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT);
 651         switch (midr) {
 652         case MIDR_CA57:
 653                 str = cpu_ca57;
 654                 break;
 655         case MIDR_CA53:
 656                 str = cpu_ca53;
 657                 break;
 658         default:
 659                 str = unknown;
 660                 break;
 661         }
 662
 663         NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str,
 664                version_of_renesas);
 665
 666         reg = mmio_read_32(RCAR_PRR);
 667         product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
 668         product = reg & RCAR_PRODUCT_MASK;
 669
 670         switch (product) {
 671         case RCAR_PRODUCT_H3:
 672                 str = product_h3;
 673                 break;
 674         case RCAR_PRODUCT_M3:
 675                 str = product_m3;
 676                 break;
 677         case RCAR_PRODUCT_M3N:
 678                 str = product_m3n;
 679                 break;
 680         case RCAR_PRODUCT_E3:
 681                 str = product_e3;
 682                 break;
 683         default:
 684                 str = unknown;
 685                 break;
 686         }
 687
 688         if (RCAR_PRODUCT_M3_CUT11 == product_cut) {
 689                 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str);
 690         } else {
 691                 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
 692                 major = major + RCAR_MAJOR_OFFSET;
 693                 minor = reg & RCAR_MINOR_MASK;
 694                 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
 695         }
 696
 697         if (product == RCAR_PRODUCT_E3) {
 698                 reg = mmio_read_32(RCAR_MODEMR);
 699                 sscg = reg & RCAR_SSCG_MASK;
 700                 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
 701                 NOTICE("BL2: %s\n", str);
 702         }
 703
 704         rcar_get_board_type(&type, &rev);
 705
 706         switch (type) {
 707         case BOARD_SALVATOR_X:
 708         case BOARD_KRIEK:
 709         case BOARD_STARTER_KIT:
 710         case BOARD_SALVATOR_XS:
 711         case BOARD_EBISU:
 712         case BOARD_STARTER_KIT_PRE:
 713         case BOARD_EBISU_4D:
 714                 break;
 715         default:
 716                 type = BOARD_UNKNOWN;
 717                 break;
 718         }
 719
 720         if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN)
 721                 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type));
 722         else {
 723                 NOTICE("BL2: Board is %s Rev.%d.%d\n",
 724                        GET_BOARD_NAME(type),
 725                        GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev));
 726         }
 727
 728 #if RCAR_LSI != RCAR_AUTO
 729         if (product != TARGET_PRODUCT) {
 730                 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME);
 731                 ERROR("BL2: Please write the correct IPL to flash memory.\n");
 732                 panic();
 733         }
 734 #endif
 735         rcar_avs_init();
 736         rcar_avs_setting();
 737
 738         switch (boot_dev) {
 739         case MODEMR_BOOT_DEV_HYPERFLASH160:
 740                 str = boot_hyper160;
 741                 break;
 742         case MODEMR_BOOT_DEV_HYPERFLASH80:
 743                 str = boot_hyper80;
 744                 break;
 745         case MODEMR_BOOT_DEV_QSPI_FLASH40:
 746                 str = boot_qspi40;
 747                 break;
 748         case MODEMR_BOOT_DEV_QSPI_FLASH80:
 749                 str = boot_qspi80;
 750                 break;
 751         case MODEMR_BOOT_DEV_EMMC_25X1:
 752                 str = boot_emmc25x1;
 753                 break;
 754         case MODEMR_BOOT_DEV_EMMC_50X8:
 755                 str = boot_emmc50x8;
 756                 break;
 757         default:
 758                 str = unknown;
 759                 break;
 760         }
 761         NOTICE("BL2: Boot device is %s\n", str);
 762
 763         rcar_avs_setting();
 764         reg = rcar_rom_get_lcs(&lcs);
 765         if (reg) {
 766                 str = unknown;
 767                 goto lcm_state;
 768         }
 769
 770         switch (lcs) {
 771         case LCS_CM:
 772                 str = lcs_cm;
 773                 break;
 774         case LCS_DM:
 775                 str = lcs_dm;
 776                 break;
 777         case LCS_SD:
 778                 str = lcs_sd;
 779                 break;
 780         case LCS_SE:
 781                 str = lcs_secure;
 782                 break;
 783         case LCS_FA:
 784                 str = lcs_fa;
 785                 break;
 786         default:
 787                 str = unknown;
 788                 break;
 789         }
 790
 791 lcm_state:
 792         NOTICE("BL2: LCM state is %s\n", str);
 793
 794         rcar_avs_end();
 795         is_ddr_backup_mode();
 796
 797         bl2_tzram_layout.total_base = BL31_BASE;
 798         bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE;
 799
 800         if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
 801             boot_cpu == MODEMR_BOOT_CPU_CA53) {
 802                 ret = rcar_dram_init();
 803                 if (ret) {
 804                         NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
 805                         panic();
 806                 }
 807                 rcar_qos_init();
 808         }
 809
 810         /* Set up FDT */
 811         ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob));
 812         if (ret) {
 813                 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret);
 814                 panic();
 815         }
 816
 817         /* Add platform compatible string */
 818         bl2_populate_compatible_string(fdt);
 819
 820         /* Print DRAM layout */
 821         bl2_advertise_dram_size(product);
 822
 823         if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
 824             boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
 825                 if (rcar_emmc_init() != EMMC_SUCCESS) {
 826                         NOTICE("BL2: Failed to eMMC driver initialize.\n");
 827                         panic();
 828                 }
 829                 rcar_emmc_memcard_power(EMMC_POWER_ON);
 830                 if (rcar_emmc_mount() != EMMC_SUCCESS) {
 831                         NOTICE("BL2: Failed to eMMC mount operation.\n");
 832                         panic();
 833                 }
 834         } else {
 835                 rcar_rpc_init();
 836                 rcar_dma_init();
 837         }
 838
 839         reg = mmio_read_32(RST_WDTRSTCR);
 840         reg &= ~WDTRSTCR_RWDT_RSTMSK;
 841         reg |= WDTRSTCR_PASSWORD;
 842         mmio_write_32(RST_WDTRSTCR, reg);
 843
 844         mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD);
 845         mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
 846
 847         reg = mmio_read_32(RCAR_PRR);
 848         if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57)
 849                 mmio_write_32(CPG_CA57DBGRCR,
 850                               DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR));
 851
 852         if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53)
 853                 mmio_write_32(CPG_CA53DBGRCR,
 854                               DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
 855
 856         if (product_cut == RCAR_PRODUCT_H3_CUT10) {
 857                 reg = mmio_read_32(CPG_PLL2CR);
 858                 reg &= ~((uint32_t) 1 << 5);
 859                 mmio_write_32(CPG_PLL2CR, reg);
 860
 861                 reg = mmio_read_32(CPG_PLL4CR);
 862                 reg &= ~((uint32_t) 1 << 5);
 863                 mmio_write_32(CPG_PLL4CR, reg);
 864
 865                 reg = mmio_read_32(CPG_PLL0CR);
 866                 reg &= ~((uint32_t) 1 << 12);
 867                 mmio_write_32(CPG_PLL0CR, reg);
 868         }
 869 #if (RCAR_LOSSY_ENABLE == 1)
 870         NOTICE("BL2: Lossy Decomp areas\n");
 871
 872         fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory");
 873         if (fcnlnode < 0) {
 874                 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n",
 875                         fcnlnode);
 876                 panic();
 877         }
 878
 879         bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0,
 880                           LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode);
 881         bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1,
 882                           LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode);
 883         bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2,
 884                           LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode);
 885 #endif
 886
 887         fdt_pack(fdt);
 888         NOTICE("BL2: FDT at %p\n", fdt);
 889
 890         if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
 891             boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
 892                 rcar_io_emmc_setup();
 893         else
 894                 rcar_io_setup();
 895 }
 896
 897 void bl2_el3_plat_arch_setup(void)
 898 {
 899 #if RCAR_BL2_DCACHE == 1
 900         NOTICE("BL2: D-Cache enable\n");
 901         rcar_configure_mmu_el3(BL2_BASE,
 902                                RCAR_SYSRAM_LIMIT - BL2_BASE,
 903                                BL2_RO_BASE, BL2_RO_LIMIT
 904 #if USE_COHERENT_MEM
 905                                , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
 906 #endif
 907             );
 908 #endif
 909 }
 910
 911 void bl2_platform_setup(void)
 912 {
 913
 914 }