plat/renesas/rcar/bl31_plat_setup.c

   1 /*
   2  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
   3  * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
   4  *
   5  * SPDX-License-Identifier: BSD-3-Clause
   6  */
   7
   8 #include <stddef.h>
   9
  10 #include <arch.h>
  11 #include <arch_helpers.h>
  12 #include <bl31/bl31.h>
  13 #include <common/bl_common.h>
  14 #include <common/debug.h>
  15 #include <drivers/arm/cci.h>
  16 #include <drivers/console.h>
  17 #include <lib/mmio.h>
  18 #include <plat/common/platform.h>
  19
  20 #include "pwrc.h"
  21 #include "rcar_def.h"
  22 #include "rcar_private.h"
  23 #include "rcar_version.h"
  24
  25 IMPORT_SYM(uint64_t, __RO_START__, BL31_RO_BASE)
  26 IMPORT_SYM(uint64_t, __RO_END__, BL31_RO_LIMIT)
  27
  28 #if USE_COHERENT_MEM
  29 IMPORT_SYM(uint64_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_BASE)
  30 IMPORT_SYM(uint64_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_LIMIT)
  31 #endif
  32
  33 extern void plat_rcar_gic_driver_init(void);
  34 extern void plat_rcar_gic_init(void);
  35
  36 u_register_t rcar_boot_mpidr;
  37
  38 static int cci_map[] = {
  39         CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3,
  40         CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3
  41 };
  42
  43 void plat_cci_init(void)
  44 {
  45         uint32_t prd;
  46
  47         prd = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
  48
  49         if (RCAR_PRODUCT_H3_CUT10 == prd || RCAR_PRODUCT_H3_CUT11 == prd) {
  50                 cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX;
  51                 cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX;
  52         }
  53
  54         cci_init(RCAR_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
  55 }
  56
  57 void plat_cci_enable(void)
  58 {
  59         cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
  60 }
  61
  62 void plat_cci_disable(void)
  63 {
  64         cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
  65 }
  66
  67 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  68 {
  69         bl2_to_bl31_params_mem_t *from_bl2 = (bl2_to_bl31_params_mem_t *)
  70                                              PARAMS_BASE;
  71         entry_point_info_t *next_image_info;
  72
  73         next_image_info = (type == NON_SECURE) ?
  74                 &from_bl2->bl33_ep_info : &from_bl2->bl32_ep_info;
  75
  76         return next_image_info->pc ? next_image_info : NULL;
  77 }
  78
  79 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
  80                                 u_register_t arg2, u_register_t arg3)
  81 {
  82         /* dummy config: the actual console configuration (platform specific)
  83            is done in the driver (scif.c) */
  84         console_init(1, 0, 0);
  85
  86         NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
  87
  88         if (RCAR_CLUSTER_A53A57 == rcar_pwrc_get_cluster()) {
  89                 plat_cci_init();
  90                 plat_cci_enable();
  91         }
  92 }
  93
  94 void bl31_plat_arch_setup(void)
  95 {
  96         rcar_configure_mmu_el3(BL31_BASE,
  97                                BL31_LIMIT - BL31_BASE,
  98                                BL31_RO_BASE, BL31_RO_LIMIT
  99 #if USE_COHERENT_MEM
 100                                , BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
 101 #endif
 102             );
 103 }
 104
 105 void bl31_platform_setup(void)
 106 {
 107         plat_rcar_gic_driver_init();
 108         plat_rcar_gic_init();
 109
 110         /* enable the system level generic timer */
 111         mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
 112
 113         rcar_pwrc_setup();
 114 #if 0
 115         /* TODO: there is a broad number of rcar-gen3 SoC configurations; to
 116            support all of them, Renesas use the pwrc driver to discover what
 117            cores are on/off before announcing the topology.
 118            This code hasnt been ported yet
 119            */
 120
 121         rcar_setup_topology();
 122 #endif
 123
 124         /* mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
 125            identified during cpuhotplug (check the kernel's psci migrate set of
 126            functions */
 127         rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU;
 128 }