plat/rockchip/common/include/plat_private.h

   1 /*
   2  * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef PLAT_PRIVATE_H
   8 #define PLAT_PRIVATE_H
   9
  10 #ifndef __ASSEMBLY__
  11 #include <mmio.h>
  12 #include <psci.h>
  13 #include <stdint.h>
  14 #include <xlat_tables.h>
  15
  16 #define __sramdata __attribute__((section(".sram.data")))
  17 #define __sramconst __attribute__((section(".sram.rodata")))
  18 #define __sramfunc __attribute__((section(".sram.text")))
  19
  20 #define __pmusramdata __attribute__((section(".pmusram.data")))
  21 #define __pmusramconst __attribute__((section(".pmusram.rodata")))
  22 #define __pmusramfunc __attribute__((section(".pmusram.text")))
  23
  24 extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
  25 extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
  26 extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end;
  27 extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end;
  28 extern uint32_t __sram_incbin_start, __sram_incbin_end;
  29 extern uint32_t __sram_incbin_real_end;
  30
  31 struct rockchip_bl31_params {
  32        param_header_t h;
  33        image_info_t *bl31_image_info;
  34        entry_point_info_t *bl32_ep_info;
  35        image_info_t *bl32_image_info;
  36        entry_point_info_t *bl33_ep_info;
  37        image_info_t *bl33_image_info;
  38 };
  39
  40 /******************************************************************************
  41  * The register have write-mask bits, it is mean, if you want to set the bits,
  42  * you needs set the write-mask bits at the same time,
  43  * The write-mask bits is in high 16-bits.
  44  * The fllowing macro definition helps access write-mask bits reg efficient!
  45  ******************************************************************************/
  46 #define REG_MSK_SHIFT   16
  47
  48 #ifndef WMSK_BIT
  49 #define WMSK_BIT(nr)            BIT((nr) + REG_MSK_SHIFT)
  50 #endif
  51
  52 /* set one bit with write mask */
  53 #ifndef BIT_WITH_WMSK
  54 #define BIT_WITH_WMSK(nr)       (BIT(nr) | WMSK_BIT(nr))
  55 #endif
  56
  57 #ifndef BITS_SHIFT
  58 #define BITS_SHIFT(bits, shift) (bits << (shift))
  59 #endif
  60
  61 #ifndef BITS_WITH_WMASK
  62 #define BITS_WITH_WMASK(bits, msk, shift)\
  63         (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
  64 #endif
  65
  66 /******************************************************************************
  67  * Function and variable prototypes
  68  *****************************************************************************/
  69 void plat_configure_mmu_el3(unsigned long total_base,
  70                             unsigned long total_size,
  71                             unsigned long,
  72                             unsigned long,
  73                             unsigned long,
  74                             unsigned long);
  75
  76 void plat_cci_init(void);
  77 void plat_cci_enable(void);
  78 void plat_cci_disable(void);
  79
  80 void plat_delay_timer_init(void);
  81
  82 void params_early_setup(void *plat_params_from_bl2);
  83
  84 void plat_rockchip_gic_driver_init(void);
  85 void plat_rockchip_gic_init(void);
  86 void plat_rockchip_gic_cpuif_enable(void);
  87 void plat_rockchip_gic_cpuif_disable(void);
  88 void plat_rockchip_gic_pcpu_init(void);
  89
  90 void plat_rockchip_pmu_init(void);
  91 void plat_rockchip_soc_init(void);
  92 uintptr_t plat_get_sec_entrypoint(void);
  93
  94 void platform_cpu_warmboot(void);
  95
  96 struct gpio_info *plat_get_rockchip_gpio_reset(void);
  97 struct gpio_info *plat_get_rockchip_gpio_poweroff(void);
  98 struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
  99 struct apio_info *plat_get_rockchip_suspend_apio(void);
 100 void plat_rockchip_gpio_init(void);
 101 void plat_rockchip_save_gpio(void);
 102 void plat_rockchip_restore_gpio(void);
 103
 104 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint);
 105 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
 106                                  plat_local_state_t lvl_state);
 107 int rockchip_soc_cores_pwr_dm_off(void);
 108 int rockchip_soc_sys_pwr_dm_suspend(void);
 109 int rockchip_soc_cores_pwr_dm_suspend(void);
 110 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
 111                                      plat_local_state_t lvl_state);
 112 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
 113                                        plat_local_state_t lvl_state);
 114 int rockchip_soc_cores_pwr_dm_on_finish(void);
 115 int rockchip_soc_sys_pwr_dm_resume(void);
 116
 117 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
 118                                     plat_local_state_t lvl_state);
 119 int rockchip_soc_cores_pwr_dm_resume(void);
 120 void __dead2 rockchip_soc_soft_reset(void);
 121 void __dead2 rockchip_soc_system_off(void);
 122 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
 123                                 const psci_power_state_t *target_state);
 124 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void);
 125
 126 extern const unsigned char rockchip_power_domain_tree_desc[];
 127
 128 extern void *pmu_cpuson_entrypoint;
 129 extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT];
 130 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
 131
 132 extern const mmap_region_t plat_rk_mmap[];
 133
 134 void rockchip_plat_mmu_el3(void);
 135
 136 #endif /* __ASSEMBLY__ */
 137
 138 /******************************************************************************
 139  * cpu up status
 140  * The bits of macro value is not more than 12 bits for cmp instruction!
 141  ******************************************************************************/
 142 #define PMU_CPU_HOTPLUG         0xf00
 143 #define PMU_CPU_AUTO_PWRDN      0xf0
 144 #define PMU_CLST_RET    0xa5
 145
 146 #endif /* PLAT_PRIVATE_H */