2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
10 #include <platform_def.h>
12 #include <arch_helpers.h>
13 #include <bl31/bl31.h>
14 #include <common/debug.h>
15 #include <drivers/console.h>
16 #include <drivers/delay_timer.h>
17 #include <lib/bakery_lock.h>
19 #include <plat/common/platform.h>
21 #include <plat_private.h>
24 #include <rk3328_def.h>
26 DEFINE_BAKERY_LOCK(rockchip_pd_lock
);
28 static struct rk3328_sleep_ddr_data ddr_data
;
29 static __sramdata
struct rk3328_sleep_sram_data sram_data
;
31 static uint32_t cpu_warm_boot_addr
;
33 #pragma weak rk3328_pmic_suspend
34 #pragma weak rk3328_pmic_resume
36 static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id
)
38 uint32_t pd_reg
, apm_reg
;
40 pd_reg
= mmio_read_32(PMU_BASE
+ PMU_PWRDN_CON
) & BIT(cpu_id
);
41 apm_reg
= mmio_read_32(PMU_BASE
+ PMU_CPUAPM_CON(cpu_id
)) &
44 if (pd_reg
&& !apm_reg
)
46 else if (!pd_reg
&& apm_reg
)
49 ERROR("%s: 0x%x, 0x%x\n", __func__
, pd_reg
, apm_reg
);
54 static int cpus_power_domain_on(uint32_t cpu_id
)
56 uint32_t cpu_pd
, cfg_info
;
58 cpu_pd
= PD_CPU0
+ cpu_id
;
59 cfg_info
= get_cpus_pwr_domain_cfg_info(cpu_id
);
61 if (cfg_info
== core_pwr_pd
) {
63 mmio_write_32(PMU_BASE
+ PMU_CPUAPM_CON(cpu_id
),
66 /* if the cores have be on, power off it firstly */
67 if (pmu_power_domain_st(cpu_pd
) == pmu_pd_on
) {
68 mmio_write_32(PMU_BASE
+ PMU_CPUAPM_CON(cpu_id
),
70 pmu_power_domain_ctr(cpu_pd
, pmu_pd_off
);
72 pmu_power_domain_ctr(cpu_pd
, pmu_pd_on
);
74 if (pmu_power_domain_st(cpu_pd
) == pmu_pd_on
) {
75 WARN("%s: cpu%d is not in off,!\n", __func__
, cpu_id
);
79 mmio_write_32(PMU_BASE
+ PMU_CPUAPM_CON(cpu_id
),
80 BIT(core_pm_sft_wakeup_en
));
86 static int cpus_power_domain_off(uint32_t cpu_id
, uint32_t pd_cfg
)
88 uint32_t cpu_pd
, core_pm_value
;
90 cpu_pd
= PD_CPU0
+ cpu_id
;
91 if (pmu_power_domain_st(cpu_pd
) == pmu_pd_off
)
94 if (pd_cfg
== core_pwr_pd
) {
95 if (check_cpu_wfie(cpu_id
, CKECK_WFEI_MSK
))
98 mmio_write_32(PMU_BASE
+ PMU_CPUAPM_CON(cpu_id
),
100 pmu_power_domain_ctr(cpu_pd
, pmu_pd_off
);
102 core_pm_value
= BIT(core_pm_en
) | BIT(core_pm_dis_int
);
103 if (pd_cfg
== core_pwr_wfi_int
)
104 core_pm_value
|= BIT(core_pm_int_wakeup_en
);
106 mmio_write_32(PMU_BASE
+ PMU_CPUAPM_CON(cpu_id
),
113 static void nonboot_cpus_off(void)
115 uint32_t boot_cpu
, cpu
;
117 /* turn off noboot cpus */
118 boot_cpu
= plat_my_core_pos();
119 for (cpu
= 0; cpu
< PLATFORM_CORE_COUNT
; cpu
++) {
122 cpus_power_domain_off(cpu
, core_pwr_pd
);
128 /* TODO: support the sdram save for rk3328 SoCs*/
131 void sram_restore(void)
133 /* TODO: support the sdram restore for rk3328 SoCs */
136 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr
, uint64_t entrypoint
)
138 uint32_t cpu_id
= plat_core_pos_by_mpidr(mpidr
);
140 assert(cpu_id
< PLATFORM_CORE_COUNT
);
141 assert(cpuson_flags
[cpu_id
] == 0);
142 cpuson_flags
[cpu_id
] = PMU_CPU_HOTPLUG
;
143 cpuson_entry_point
[cpu_id
] = entrypoint
;
146 cpus_power_domain_on(cpu_id
);
151 int rockchip_soc_cores_pwr_dm_off(void)
153 uint32_t cpu_id
= plat_my_core_pos();
155 cpus_power_domain_off(cpu_id
, core_pwr_wfi
);
160 int rockchip_soc_cores_pwr_dm_suspend(void)
162 uint32_t cpu_id
= plat_my_core_pos();
164 assert(cpu_id
< PLATFORM_CORE_COUNT
);
165 assert(cpuson_flags
[cpu_id
] == 0);
166 cpuson_flags
[cpu_id
] = PMU_CPU_AUTO_PWRDN
;
167 cpuson_entry_point
[cpu_id
] = (uintptr_t)plat_get_sec_entrypoint();
170 cpus_power_domain_off(cpu_id
, core_pwr_wfi_int
);
175 int rockchip_soc_cores_pwr_dm_on_finish(void)
177 uint32_t cpu_id
= plat_my_core_pos();
179 mmio_write_32(PMU_BASE
+ PMU_CPUAPM_CON(cpu_id
), CORES_PM_DISABLE
);
184 int rockchip_soc_cores_pwr_dm_resume(void)
186 uint32_t cpu_id
= plat_my_core_pos();
188 mmio_write_32(PMU_BASE
+ PMU_CPUAPM_CON(cpu_id
), CORES_PM_DISABLE
);
193 void __dead2
rockchip_soc_soft_reset(void)
195 mmio_write_32(CRU_BASE
+ CRU_CRU_MODE
, PLL_SLOW_MODE(CPLL_ID
));
196 mmio_write_32(CRU_BASE
+ CRU_CRU_MODE
, PLL_SLOW_MODE(GPLL_ID
));
197 mmio_write_32(CRU_BASE
+ CRU_CRU_MODE
, PLL_SLOW_MODE(NPLL_ID
));
198 mmio_write_32(CRU_BASE
+ CRU_CRU_MODE
, PLL_SLOW_MODE(APLL_ID
));
201 mmio_write_32(CRU_BASE
+ CRU_GLB_SRST_FST
, CRU_GLB_SRST_FST_VALUE
);
204 * Maybe the HW needs some times to reset the system,
205 * so we do not hope the core to excute valid codes.
212 * For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328.
213 * If the PMIC is configed for responding the sleep pin to power off it,
214 * once the pin is output high, it will get the pmic power off.
216 void __dead2
rockchip_soc_system_off(void)
221 val
= mmio_read_32(GRF_BASE
+ GRF_GPIO2D_IOMUX
);
222 val
&= ~GPIO2_D2_GPIO_MODE
;
223 mmio_write_32(GRF_BASE
+ GRF_GPIO2D_IOMUX
, val
);
226 val
= mmio_read_32(GPIO2_BASE
+ SWPORTA_DDR
);
228 mmio_write_32(GPIO2_BASE
+ SWPORTA_DDR
, val
);
230 /* config output high level */
231 val
= mmio_read_32(GPIO2_BASE
);
233 mmio_write_32(GPIO2_BASE
, val
);
240 static uint32_t clk_ungt_msk
[CRU_CLKGATE_NUMS
] = {
241 0x187f, 0x0000, 0x010c, 0x0000, 0x0200,
242 0x0010, 0x0000, 0x0017, 0x001f, 0x0000,
243 0x0000, 0x0000, 0x0000, 0x0003, 0x0000,
244 0xf001, 0x27c0, 0x04D9, 0x03ff, 0x0000,
245 0x0000, 0x0000, 0x0010, 0x0000, 0x0000,
246 0x0000, 0x0000, 0x0003, 0x0008
249 static void clks_gating_suspend(uint32_t *ungt_msk
)
253 for (i
= 0; i
< CRU_CLKGATE_NUMS
; i
++) {
254 ddr_data
.clk_ungt_save
[i
] =
255 mmio_read_32(CRU_BASE
+ CRU_CLKGATE_CON(i
));
256 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(i
),
257 ((~ungt_msk
[i
]) << 16) | 0xffff);
261 static void clks_gating_resume(void)
265 for (i
= 0; i
< CRU_CLKGATE_NUMS
; i
++)
266 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(i
),
267 ddr_data
.clk_ungt_save
[i
] | 0xffff0000);
270 static inline void pm_pll_wait_lock(uint32_t pll_id
)
272 uint32_t delay
= PLL_LOCKED_TIMEOUT
;
275 if (mmio_read_32(CRU_BASE
+ PLL_CONS(pll_id
, 1)) &
281 ERROR("lock-pll: %d\n", pll_id
);
284 static inline void pll_pwr_dwn(uint32_t pll_id
, uint32_t pd
)
286 mmio_write_32(CRU_BASE
+ PLL_CONS(pll_id
, 1),
287 BITS_WITH_WMASK(1, 1, 15));
289 mmio_write_32(CRU_BASE
+ PLL_CONS(pll_id
, 1),
290 BITS_WITH_WMASK(1, 1, 14));
292 mmio_write_32(CRU_BASE
+ PLL_CONS(pll_id
, 1),
293 BITS_WITH_WMASK(0, 1, 14));
296 static __sramfunc
void dpll_suspend(void)
301 mmio_write_32(CRU_BASE
+ CRU_CRU_MODE
, PLL_SLOW_MODE(DPLL_ID
));
304 for (i
= 0; i
< CRU_PLL_CON_NUMS
; i
++)
305 sram_data
.dpll_con_save
[i
] =
306 mmio_read_32(CRU_BASE
+ PLL_CONS(DPLL_ID
, i
));
307 mmio_write_32(CRU_BASE
+ PLL_CONS(DPLL_ID
, 1),
308 BITS_WITH_WMASK(1, 1, 15));
309 mmio_write_32(CRU_BASE
+ PLL_CONS(DPLL_ID
, 1),
310 BITS_WITH_WMASK(1, 1, 14));
313 static __sramfunc
void dpll_resume(void)
315 uint32_t delay
= PLL_LOCKED_TIMEOUT
;
317 mmio_write_32(CRU_BASE
+ PLL_CONS(DPLL_ID
, 1),
318 BITS_WITH_WMASK(1, 1, 15));
319 mmio_write_32(CRU_BASE
+ PLL_CONS(DPLL_ID
, 1),
320 BITS_WITH_WMASK(0, 1, 14));
321 mmio_write_32(CRU_BASE
+ PLL_CONS(DPLL_ID
, 1),
322 sram_data
.dpll_con_save
[1] | 0xc0000000);
327 if (mmio_read_32(CRU_BASE
+ PLL_CONS(DPLL_ID
, 1)) &
336 mmio_write_32(CRU_BASE
+ CRU_CRU_MODE
,
337 PLL_NORM_MODE(DPLL_ID
));
340 static inline void pll_suspend(uint32_t pll_id
)
345 mmio_write_32(CRU_BASE
+ CRU_CRU_MODE
, PLL_SLOW_MODE(pll_id
));
348 for (i
= 0; i
< CRU_PLL_CON_NUMS
; i
++)
349 ddr_data
.cru_plls_con_save
[pll_id
][i
] =
350 mmio_read_32(CRU_BASE
+ PLL_CONS(pll_id
, i
));
353 pll_pwr_dwn(pll_id
, pmu_pd_off
);
356 static inline void pll_resume(uint32_t pll_id
)
358 mmio_write_32(CRU_BASE
+ PLL_CONS(pll_id
, 1),
359 ddr_data
.cru_plls_con_save
[pll_id
][1] | 0xc0000000);
361 pm_pll_wait_lock(pll_id
);
363 if (PLL_IS_NORM_MODE(ddr_data
.cru_mode_save
, pll_id
))
364 mmio_write_32(CRU_BASE
+ CRU_CRU_MODE
,
365 PLL_NORM_MODE(pll_id
));
368 static void pm_plls_suspend(void)
370 ddr_data
.cru_mode_save
= mmio_read_32(CRU_BASE
+ CRU_CRU_MODE
);
371 ddr_data
.clk_sel0
= mmio_read_32(CRU_BASE
+ CRU_CLKSEL_CON(0));
372 ddr_data
.clk_sel1
= mmio_read_32(CRU_BASE
+ CRU_CLKSEL_CON(1));
373 ddr_data
.clk_sel18
= mmio_read_32(CRU_BASE
+ CRU_CLKSEL_CON(18));
374 ddr_data
.clk_sel20
= mmio_read_32(CRU_BASE
+ CRU_CLKSEL_CON(20));
375 ddr_data
.clk_sel24
= mmio_read_32(CRU_BASE
+ CRU_CLKSEL_CON(24));
376 ddr_data
.clk_sel38
= mmio_read_32(CRU_BASE
+ CRU_CLKSEL_CON(38));
377 pll_suspend(NPLL_ID
);
378 pll_suspend(CPLL_ID
);
379 pll_suspend(GPLL_ID
);
380 pll_suspend(APLL_ID
);
383 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(0),
384 BITS_WITH_WMASK(0, 0x1f, 0));
387 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(1),
388 BITS_WITH_WMASK(0, 0xf, 0));
391 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(20),
392 BITS_WITH_WMASK(0, 0x1f, 0));
395 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(24),
396 BITS_WITH_WMASK(0, 0x7f, 8));
399 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(18),
400 BITS_WITH_WMASK(2, 0x3, 8));
403 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(38),
404 BITS_WITH_WMASK(767, 0x3fff, 0) |
405 BITS_WITH_WMASK(2, 0x3, 14));
408 static void pm_plls_resume(void)
411 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(38),
413 BITS_WMSK(0x3fff, 0) |
417 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(18),
418 ddr_data
.clk_sel18
| BITS_WMSK(0x3, 8));
421 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(24),
422 ddr_data
.clk_sel24
| BITS_WMSK(0x7f, 8));
425 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(20),
426 ddr_data
.clk_sel20
| BITS_WMSK(0x1f, 0));
429 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(1),
430 ddr_data
.clk_sel1
| BITS_WMSK(0xf, 0));
433 mmio_write_32(CRU_BASE
+ CRU_CLKSEL_CON(0),
434 ddr_data
.clk_sel0
| BITS_WMSK(0x1f, 0));
436 pll_pwr_dwn(APLL_ID
, pmu_pd_on
);
437 pll_pwr_dwn(GPLL_ID
, pmu_pd_on
);
438 pll_pwr_dwn(CPLL_ID
, pmu_pd_on
);
439 pll_pwr_dwn(NPLL_ID
, pmu_pd_on
);
447 #define ARCH_TIMER_TICKS_PER_US (SYS_COUNTER_FREQ_IN_TICKS / 1000000)
449 static __sramfunc
void sram_udelay(uint32_t us
)
451 uint64_t pct_orig
, pct_now
;
452 uint64_t to_wait
= ARCH_TIMER_TICKS_PER_US
* us
;
455 pct_orig
= read_cntpct_el0();
459 pct_now
= read_cntpct_el0();
460 } while ((pct_now
- pct_orig
) <= to_wait
);
464 * For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328.
465 * If the PMIC is configed for responding the sleep pin
466 * to get it into sleep mode,
467 * once the pin is output high, it will get the pmic into sleep mode.
469 __sramfunc
void rk3328_pmic_suspend(void)
471 sram_data
.pmic_sleep_save
= mmio_read_32(GRF_BASE
+ PMIC_SLEEP_REG
);
472 sram_data
.pmic_sleep_gpio_save
[1] = mmio_read_32(GPIO2_BASE
+ 4);
473 sram_data
.pmic_sleep_gpio_save
[0] = mmio_read_32(GPIO2_BASE
);
474 mmio_write_32(GRF_BASE
+ PMIC_SLEEP_REG
, BITS_WITH_WMASK(0, 0x3, 4));
475 mmio_write_32(GPIO2_BASE
+ 4,
476 sram_data
.pmic_sleep_gpio_save
[1] | BIT(26));
477 mmio_write_32(GPIO2_BASE
,
478 sram_data
.pmic_sleep_gpio_save
[0] | BIT(26));
481 __sramfunc
void rk3328_pmic_resume(void)
483 mmio_write_32(GPIO2_BASE
, sram_data
.pmic_sleep_gpio_save
[0]);
484 mmio_write_32(GPIO2_BASE
+ 4, sram_data
.pmic_sleep_gpio_save
[1]);
485 mmio_write_32(GRF_BASE
+ PMIC_SLEEP_REG
,
486 sram_data
.pmic_sleep_save
| BITS_WMSK(0xffff, 0));
487 /* Resuming volt need a lot of time */
491 static __sramfunc
void ddr_suspend(void)
493 sram_data
.pd_sr_idle_save
= mmio_read_32(DDR_UPCTL_BASE
+
495 sram_data
.pd_sr_idle_save
&= SELFREF_EN
;
497 mmio_clrbits_32(DDR_UPCTL_BASE
+ DDR_PCTL2_PWRCTL
, SELFREF_EN
);
498 sram_data
.ddr_grf_con0
= mmio_read_32(DDR_GRF_BASE
+
500 mmio_write_32(DDR_GRF_BASE
, BIT_WITH_WMSK(14) | WMSK_BIT(15));
503 * Override csysreq from ddrc and
504 * send valid csysreq signal to PMU,
505 * csysreq is controlled by ddrc only
508 /* in self-refresh */
509 mmio_setbits_32(PMU_BASE
+ PMU_SFT_CON
, BIT(0));
510 while ((mmio_read_32(DDR_GRF_BASE
+ DDRGRF_SOC_STATUS(1)) &
511 (0x03 << 12)) != (0x02 << 12))
514 mmio_setbits_32(PMU_BASE
+ PMU_SFT_CON
, BIT(2));
517 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(0),
518 BITS_WITH_WMASK(0x7, 0x7, 4));
519 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(7),
520 BITS_WITH_WMASK(1, 1, 4));
521 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(18),
522 BITS_WITH_WMASK(0x1ff, 0x1ff, 1));
523 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(27),
524 BITS_WITH_WMASK(0x3, 0x3, 0));
529 __sramfunc
void dmc_restore(void)
534 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(0),
535 BITS_WITH_WMASK(0, 0x7, 4));
536 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(7),
537 BITS_WITH_WMASK(0, 1, 4));
538 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(18),
539 BITS_WITH_WMASK(0, 0x1ff, 1));
540 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(27),
541 BITS_WITH_WMASK(0, 0x3, 0));
543 /* ddr de_retention */
544 mmio_clrbits_32(PMU_BASE
+ PMU_SFT_CON
, BIT(2));
545 /* exit self-refresh */
546 mmio_clrbits_32(PMU_BASE
+ PMU_SFT_CON
, BIT(0));
547 while ((mmio_read_32(DDR_GRF_BASE
+ DDRGRF_SOC_STATUS(1)) &
548 (0x03 << 12)) != (0x00 << 12))
551 mmio_write_32(DDR_GRF_BASE
, sram_data
.ddr_grf_con0
| 0xc0000000);
552 if (sram_data
.pd_sr_idle_save
)
553 mmio_setbits_32(DDR_UPCTL_BASE
+ DDR_PCTL2_PWRCTL
,
557 static __sramfunc
void sram_dbg_uart_suspend(void)
559 sram_data
.uart2_ier
= mmio_read_32(UART2_BASE
+ UART_IER
);
560 mmio_write_32(UART2_BASE
+ UART_IER
, UART_INT_DISABLE
);
561 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(16), 0x20002000);
562 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(2), 0x00040004);
565 __sramfunc
void sram_dbg_uart_resume(void)
567 /* restore uart clk and reset fifo */
568 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(16), 0x20000000);
569 mmio_write_32(CRU_BASE
+ CRU_CLKGATE_CON(2), 0x00040000);
570 mmio_write_32(UART2_BASE
+ UART_FCR
, UART_FIFO_RESET
);
571 mmio_write_32(UART2_BASE
+ UART_IER
, sram_data
.uart2_ier
);
574 static __sramfunc
void sram_soc_enter_lp(void)
578 apm_value
= BIT(core_pm_en
) |
579 BIT(core_pm_dis_int
) |
580 BIT(core_pm_int_wakeup_en
);
581 mmio_write_32(PMU_BASE
+ PMU_CPUAPM_CON(PD_CPU0
), apm_value
);
588 *Soc will enter low power mode and
589 *do not return to here.
594 __sramfunc
void sram_suspend(void)
596 /* disable mmu and icache */
597 disable_mmu_icache_el3();
602 mmio_write_32(SGRF_BASE
+ SGRF_SOC_CON(1),
603 ((uintptr_t)&pmu_cpuson_entrypoint
>> CPU_BOOT_ADDR_ALIGN
) |
604 CPU_BOOT_ADDR_WMASK
);
606 /* ddr self-refresh and gating phy */
609 rk3328_pmic_suspend();
611 sram_dbg_uart_suspend();
616 void __dead2
rockchip_soc_sys_pd_pwr_dn_wfi(void)
620 /* should never reach here */
621 psci_power_down_wfi();
624 int rockchip_soc_sys_pwr_dm_suspend(void)
626 clks_gating_suspend(clk_ungt_msk
);
633 int rockchip_soc_sys_pwr_dm_resume(void)
637 clks_gating_resume();
639 plat_rockchip_gic_cpuif_enable();
644 void rockchip_plat_mmu_el3(void)
646 /* TODO: support the el3 for rk3328 SoCs */
649 void plat_rockchip_pmu_init(void)
653 for (cpu
= 0; cpu
< PLATFORM_CORE_COUNT
; cpu
++)
654 cpuson_flags
[cpu
] = 0;
656 cpu_warm_boot_addr
= (uint64_t)platform_cpu_warmboot
;
658 /* the warm booting address of cpus */
659 mmio_write_32(SGRF_BASE
+ SGRF_SOC_CON(1),
660 (cpu_warm_boot_addr
>> CPU_BOOT_ADDR_ALIGN
) |
661 CPU_BOOT_ADDR_WMASK
);
665 INFO("%s: pd status 0x%x\n",
666 __func__
, mmio_read_32(PMU_BASE
+ PMU_PWRDN_ST
));