plat/rockchip/rk3368/include/platform_def.h

   1 /*
   2  * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef PLATFORM_DEF_H
   8 #define PLATFORM_DEF_H
   9
  10 #include <arch.h>
  11 #include <lib/utils_def.h>
  12 #include <plat/common/common_def.h>
  13
  14 #include <rk3368_def.h>
  15
  16 /*******************************************************************************
  17  * Platform binary types for linking
  18  ******************************************************************************/
  19 #define PLATFORM_LINKER_FORMAT          "elf64-littleaarch64"
  20 #define PLATFORM_LINKER_ARCH            aarch64
  21
  22 /*******************************************************************************
  23  * Generic platform constants
  24  ******************************************************************************/
  25
  26 /* Size of cacheable stacks */
  27 #if defined(IMAGE_BL1)
  28 #define PLATFORM_STACK_SIZE 0x440
  29 #elif defined(IMAGE_BL2)
  30 #define PLATFORM_STACK_SIZE 0x400
  31 #elif defined(IMAGE_BL31)
  32 #define PLATFORM_STACK_SIZE 0x800
  33 #elif defined(IMAGE_BL32)
  34 #define PLATFORM_STACK_SIZE 0x440
  35 #endif
  36
  37 #define FIRMWARE_WELCOME_STR            "Booting Trusted Firmware\n"
  38
  39 #define PLATFORM_MAX_AFFLVL             MPIDR_AFFLVL2
  40 #define PLATFORM_SYSTEM_COUNT           1
  41 #define PLATFORM_CLUSTER_COUNT          2
  42 #define PLATFORM_CLUSTER0_CORE_COUNT    4
  43 #define PLATFORM_CLUSTER1_CORE_COUNT    4
  44 #define PLATFORM_CORE_COUNT             (PLATFORM_CLUSTER1_CORE_COUNT + \
  45                                          PLATFORM_CLUSTER0_CORE_COUNT)
  46 #define PLATFORM_MAX_CPUS_PER_CLUSTER   4
  47 #define PLATFORM_NUM_AFFS               (PLATFORM_SYSTEM_COUNT +        \
  48                                          PLATFORM_CLUSTER_COUNT +       \
  49                                          PLATFORM_CORE_COUNT)
  50
  51 #define PLAT_RK_CLST_TO_CPUID_SHIFT     8
  52
  53 #define PLAT_MAX_PWR_LVL                MPIDR_AFFLVL2
  54
  55 /*
  56  * This macro defines the deepest retention state possible. A higher state
  57  * id will represent an invalid or a power down state.
  58  */
  59 #define PLAT_MAX_RET_STATE              U(1)
  60
  61 /*
  62  * This macro defines the deepest power down states possible. Any state ID
  63  * higher than this is invalid.
  64  */
  65 #define PLAT_MAX_OFF_STATE              U(2)
  66
  67 /*******************************************************************************
  68  * Platform memory map related constants
  69  ******************************************************************************/
  70 /* TF txet, ro, rw, Size: 512KB */
  71 #define TZRAM_BASE              (0x0)
  72 #define TZRAM_SIZE              (0x80000)
  73
  74 /*******************************************************************************
  75  * BL31 specific defines.
  76  ******************************************************************************/
  77 /*
  78  * Put BL3-1 at the top of the Trusted RAM
  79  */
  80 #define BL31_BASE               (TZRAM_BASE + 0x10000)
  81 #define BL31_LIMIT      (TZRAM_BASE + TZRAM_SIZE)
  82
  83 /*******************************************************************************
  84  * Platform specific page table and MMU setup constants
  85  ******************************************************************************/
  86 #define PLAT_VIRT_ADDR_SPACE_SIZE   (1ULL << 32)
  87 #define PLAT_PHY_ADDR_SPACE_SIZE    (1ULL << 32)
  88 #define MAX_XLAT_TABLES         8
  89 #define MAX_MMAP_REGIONS        16
  90
  91 /*******************************************************************************
  92  * Declarations and constants to access the mailboxes safely. Each mailbox is
  93  * aligned on the biggest cache line size in the platform. This is known only
  94  * to the platform as it might have a combination of integrated and external
  95  * caches. Such alignment ensures that two maiboxes do not sit on the same cache
  96  * line at any cache level. They could belong to different cpus/clusters &
  97  * get written while being protected by different locks causing corruption of
  98  * a valid mailbox address.
  99  ******************************************************************************/
 100 #define CACHE_WRITEBACK_SHIFT   6
 101 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
 102
 103 /*
 104  * Define GICD and GICC and GICR base
 105  */
 106 #define PLAT_RK_GICD_BASE       RK3368_GICD_BASE
 107 #define PLAT_RK_GICC_BASE       RK3368_GICC_BASE
 108
 109 #define PLAT_RK_UART_BASE       UART2_BASE
 110 #define PLAT_RK_UART_CLOCK      RK3368_UART_CLOCK
 111 #define PLAT_RK_UART_BAUDRATE   RK3368_BAUDRATE
 112
 113 #define PLAT_RK_CCI_BASE        CCI400_BASE
 114
 115 #define PLAT_RK_PRIMARY_CPU     0x0
 116
 117 #define PSRAM_DO_DDR_RESUME     0
 118 #define PSRAM_CHECK_WAKEUP_CPU  0
 119
 120 #endif /* PLATFORM_DEF_H */