plat/rockchip/rk3399/drivers/secure/secure.c

   1 /*
   2  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch_helpers.h>
   8 #include <assert.h>
   9 #include <debug.h>
  10 #include <delay_timer.h>
  11 #include <plat_private.h>
  12 #include <secure.h>
  13 #include <soc.h>
  14
  15 static void sgrf_ddr_rgn_global_bypass(uint32_t bypass)
  16 {
  17         if (bypass)
  18                 /* set bypass (non-secure regions) for whole ddr regions */
  19                 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
  20                               SGRF_DDR_RGN_BYPS);
  21         else
  22                 /* cancel bypass for whole ddr regions */
  23                 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
  24                               SGRF_DDR_RGN_NO_BYPS);
  25 }
  26
  27 /**
  28  * There are 8 + 1 regions for DDR secure control:
  29  * DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB
  30  * DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7
  31  *
  32  * DDR_RGN_0 - start address of the RGN0
  33  * DDR_RGN_8 - end address of the RGN0
  34  * DDR_RGN_1 - start address of the RGN1
  35  * DDR_RGN_9 - end address of the RGN1
  36  * ...
  37  * DDR_RGN_7 - start address of the RGN7
  38  * DDR_RGN_15 - end address of the RGN7
  39  * DDR_RGN_16 - bit 0 ~ 7 is bitmap for RGN0~7 secure,0: disable, 1: enable
  40  *              bit 8 is setting for RGNx, the rest of the memory and region
  41  *                which excludes RGN0~7, 0: disable, 1: enable
  42  *              bit 9, the global secure configuration via bypass, 0: disable
  43  *                bypass, 1: enable bypass
  44  *
  45  * @rgn - the DDR regions 0 ~ 7 which are can be configured.
  46  * The @st_mb and @ed_mb indicate the start and end addresses for which to set
  47  * the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
  48  * address range 0x0 ~ 0xfffff is secure.
  49  *
  50  * For example, if we would like to set the range [0, 32MB) is security via
  51  * DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
  52  */
  53 static void sgrf_ddr_rgn_config(uint32_t rgn,
  54                                 uintptr_t st, uintptr_t ed)
  55 {
  56         uintptr_t st_mb, ed_mb;
  57
  58         assert(rgn <= 7);
  59         assert(st < ed);
  60
  61         /* check aligned 1MB */
  62         assert(st % SIZE_M(1) == 0);
  63         assert(ed % SIZE_M(1) == 0);
  64
  65         st_mb = st / SIZE_M(1);
  66         ed_mb = ed / SIZE_M(1);
  67
  68         /* set ddr region addr start */
  69         mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn),
  70                       BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0));
  71
  72         /* set ddr region addr end */
  73         mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8),
  74                       BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0));
  75
  76         mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
  77                       BIT_WITH_WMSK(rgn));
  78 }
  79
  80 void secure_watchdog_gate(void)
  81 {
  82         /**
  83          * Disable CA53 and CM0 wdt pclk
  84          * BIT[8]: ca53 wdt pclk, 0: enable 1: disable
  85          * BIT[10]: cm0 wdt pclk, 0: enable 1: disable
  86          */
  87         mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
  88                       BIT_WITH_WMSK(PCLK_WDT_CA53_GATE_SHIFT) |
  89                       BIT_WITH_WMSK(PCLK_WDT_CM0_GATE_SHIFT));
  90 }
  91
  92 __pmusramfunc void secure_watchdog_ungate(void)
  93 {
  94         /**
  95          * Enable CA53 and CM0 wdt pclk
  96          * BIT[8]: ca53 wdt pclk, 0: enable 1: disable
  97          * BIT[10]: cm0 wdt pclk, 0: enable 1: disable
  98          */
  99         mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
 100                       WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) |
 101                       WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
 102 }
 103
 104 __pmusramfunc void sram_secure_timer_init(void)
 105 {
 106         mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
 107         mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
 108
 109         mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
 110         mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
 111
 112         /* auto reload & enable the timer */
 113         mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
 114                       TIMER_EN | TIMER_FMODE);
 115 }
 116
 117 void secure_timer_init(void)
 118 {
 119         mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
 120         mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
 121
 122         mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
 123         mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
 124
 125         /* auto reload & enable the timer */
 126         mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
 127                       TIMER_EN | TIMER_FMODE);
 128 }
 129
 130 void secure_sgrf_init(void)
 131 {
 132         /* security config for master */
 133         mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5),
 134                       REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
 135         mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6),
 136                       REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
 137         mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7),
 138                       REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
 139
 140         /* security config for slave */
 141         mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0),
 142                       SGRF_PMU_SLV_S_CFGED |
 143                       SGRF_PMU_SLV_CRYPTO1_NS);
 144         mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1),
 145                       SGRF_SLV_S_WMSK | SGRF_PMUSRAM_S);
 146         mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0),
 147                       SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
 148         mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1),
 149                       SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
 150         mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2),
 151                       SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
 152         mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3),
 153                       SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
 154         mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4),
 155                       SGRF_SLV_S_WMSK | SGRF_INTSRAM_S);
 156 }
 157
 158 void secure_sgrf_ddr_rgn_init(void)
 159 {
 160         sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE);
 161         sgrf_ddr_rgn_global_bypass(0);
 162 }