plat/rpi/common/rpi3_common.c

   1 /*
   2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8
   9 #include <platform_def.h>
  10
  11 #include <arch_helpers.h>
  12 #include <common/bl_common.h>
  13 #include <common/debug.h>
  14 #include <bl31/interrupt_mgmt.h>
  15 #include <drivers/console.h>
  16 #include <drivers/ti/uart/uart_16550.h>
  17 #include <lib/xlat_tables/xlat_tables_v2.h>
  18
  19 #include <rpi_hw.h>
  20 #include <rpi_shared.h>
  21
  22 #define MAP_DEVICE0     MAP_REGION_FLAT(DEVICE0_BASE,                   \
  23                                         DEVICE0_SIZE,                   \
  24                                         MT_DEVICE | MT_RW | MT_SECURE)
  25
  26 #ifdef SHARED_RAM_BASE
  27 #define MAP_SHARED_RAM  MAP_REGION_FLAT(SHARED_RAM_BASE,                \
  28                                         SHARED_RAM_SIZE,                \
  29                                         MT_DEVICE | MT_RW | MT_SECURE)
  30 #endif
  31
  32 #ifdef RPI3_PRELOADED_DTB_BASE
  33 #define MAP_NS_DTB      MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \
  34                                         MT_MEMORY | MT_RW | MT_NS)
  35 #endif
  36
  37 #define MAP_NS_DRAM0    MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE,   \
  38                                         MT_MEMORY | MT_RW | MT_NS)
  39
  40 #define MAP_FIP         MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE,             \
  41                                         PLAT_RPI3_FIP_MAX_SIZE,         \
  42                                         MT_MEMORY | MT_RO | MT_NS)
  43
  44 #define MAP_BL32_MEM    MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE,   \
  45                                         MT_MEMORY | MT_RW | MT_SECURE)
  46
  47 #ifdef SPD_opteed
  48 #define MAP_OPTEE_PAGEABLE      MAP_REGION_FLAT(                \
  49                                 RPI3_OPTEE_PAGEABLE_LOAD_BASE,  \
  50                                 RPI3_OPTEE_PAGEABLE_LOAD_SIZE,  \
  51                                 MT_MEMORY | MT_RW | MT_SECURE)
  52 #endif
  53
  54 /*
  55  * Table of regions for various BL stages to map using the MMU.
  56  */
  57 #ifdef IMAGE_BL1
  58 static const mmap_region_t plat_rpi3_mmap[] = {
  59 #ifdef MAP_SHARED_RAM
  60         MAP_SHARED_RAM,
  61 #endif
  62         MAP_DEVICE0,
  63         MAP_FIP,
  64 #ifdef SPD_opteed
  65         MAP_OPTEE_PAGEABLE,
  66 #endif
  67         {0}
  68 };
  69 #endif
  70
  71 #ifdef IMAGE_BL2
  72 static const mmap_region_t plat_rpi3_mmap[] = {
  73 #ifdef MAP_SHARED_RAM
  74         MAP_SHARED_RAM,
  75 #endif
  76         MAP_DEVICE0,
  77         MAP_FIP,
  78         MAP_NS_DRAM0,
  79 #ifdef BL32_BASE
  80         MAP_BL32_MEM,
  81 #endif
  82         {0}
  83 };
  84 #endif
  85
  86 #ifdef IMAGE_BL31
  87 static const mmap_region_t plat_rpi3_mmap[] = {
  88 #ifdef MAP_SHARED_RAM
  89         MAP_SHARED_RAM,
  90 #endif
  91         MAP_DEVICE0,
  92 #ifdef RPI3_PRELOADED_DTB_BASE
  93         MAP_NS_DTB,
  94 #endif
  95 #ifdef BL32_BASE
  96         MAP_BL32_MEM,
  97 #endif
  98         {0}
  99 };
 100 #endif
 101
 102 /*******************************************************************************
 103  * Function that sets up the console
 104  ******************************************************************************/
 105 static console_16550_t rpi3_console;
 106
 107 void rpi3_console_init(unsigned int base_clk_rate)
 108 {
 109         int console_scope = CONSOLE_FLAG_BOOT;
 110 #if RPI3_RUNTIME_UART != -1
 111         console_scope |= CONSOLE_FLAG_RUNTIME;
 112 #endif
 113         int rc = console_16550_register(PLAT_RPI3_UART_BASE,
 114                                         base_clk_rate,
 115                                         PLAT_RPI3_UART_BAUDRATE,
 116                                         &rpi3_console);
 117         if (rc == 0) {
 118                 /*
 119                  * The crash console doesn't use the multi console API, it uses
 120                  * the core console functions directly. It is safe to call panic
 121                  * and let it print debug information.
 122                  */
 123                 panic();
 124         }
 125
 126         console_set_scope(&rpi3_console.console, console_scope);
 127 }
 128
 129 /*******************************************************************************
 130  * Function that sets up the translation tables.
 131  ******************************************************************************/
 132 void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
 133                             uintptr_t code_start, uintptr_t code_limit,
 134                             uintptr_t rodata_start, uintptr_t rodata_limit
 135 #if USE_COHERENT_MEM
 136                             , uintptr_t coh_start, uintptr_t coh_limit
 137 #endif
 138                             )
 139 {
 140         /*
 141          * Map the Trusted SRAM with appropriate memory attributes.
 142          * Subsequent mappings will adjust the attributes for specific regions.
 143          */
 144         VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
 145                 (void *) total_base, (void *) (total_base + total_size));
 146         mmap_add_region(total_base, total_base,
 147                         total_size,
 148                         MT_MEMORY | MT_RW | MT_SECURE);
 149
 150         /* Re-map the code section */
 151         VERBOSE("Code region: %p - %p\n",
 152                 (void *) code_start, (void *) code_limit);
 153         mmap_add_region(code_start, code_start,
 154                         code_limit - code_start,
 155                         MT_CODE | MT_SECURE);
 156
 157         /* Re-map the read-only data section */
 158         VERBOSE("Read-only data region: %p - %p\n",
 159                 (void *) rodata_start, (void *) rodata_limit);
 160         mmap_add_region(rodata_start, rodata_start,
 161                         rodata_limit - rodata_start,
 162                         MT_RO_DATA | MT_SECURE);
 163
 164 #if USE_COHERENT_MEM
 165         /* Re-map the coherent memory region */
 166         VERBOSE("Coherent region: %p - %p\n",
 167                 (void *) coh_start, (void *) coh_limit);
 168         mmap_add_region(coh_start, coh_start,
 169                         coh_limit - coh_start,
 170                         MT_DEVICE | MT_RW | MT_SECURE);
 171 #endif
 172
 173         mmap_add(plat_rpi3_mmap);
 174
 175         init_xlat_tables();
 176 }
 177
 178 /*******************************************************************************
 179  * Gets SPSR for BL32 entry
 180  ******************************************************************************/
 181 uint32_t rpi3_get_spsr_for_bl32_entry(void)
 182 {
 183         /*
 184          * The Secure Payload Dispatcher service is responsible for
 185          * setting the SPSR prior to entry into the BL32 image.
 186          */
 187         return 0;
 188 }
 189
 190 /*******************************************************************************
 191  * Gets SPSR for BL33 entry
 192  ******************************************************************************/
 193 uint32_t rpi3_get_spsr_for_bl33_entry(void)
 194 {
 195 #if RPI3_BL33_IN_AARCH32
 196         INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n");
 197         return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE,
 198                            DISABLE_ALL_EXCEPTIONS);
 199 #else
 200         return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
 201 #endif
 202 }
 203
 204 unsigned int plat_get_syscnt_freq2(void)
 205 {
 206         return SYS_COUNTER_FREQ_IN_TICKS;
 207 }
 208
 209 uint32_t plat_ic_get_pending_interrupt_type(void)
 210 {
 211         ERROR("rpi3: Interrupt routed to EL3.\n");
 212         return INTR_TYPE_INVAL;
 213 }
 214
 215 uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
 216 {
 217         assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) ||
 218                (type == INTR_TYPE_NS));
 219
 220         assert(sec_state_is_valid(security_state));
 221
 222         /* Non-secure interrupts are signalled on the IRQ line always. */
 223         if (type == INTR_TYPE_NS)
 224                 return __builtin_ctz(SCR_IRQ_BIT);
 225
 226         /* Secure interrupts are signalled on the FIQ line always. */
 227         return  __builtin_ctz(SCR_FIQ_BIT);
 228 }