plat/rpi/rpi4/rpi4_bl31_setup.c

   1 /*
   2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8
   9 #include <libfdt.h>
  10
  11 #include <platform_def.h>
  12 #include <common/bl_common.h>
  13 #include <lib/mmio.h>
  14 #include <lib/xlat_tables/xlat_mmu_helpers.h>
  15 #include <lib/xlat_tables/xlat_tables_defs.h>
  16 #include <lib/xlat_tables/xlat_tables_v2.h>
  17 #include <plat/common/platform.h>
  18
  19 #include <drivers/arm/gicv2.h>
  20
  21 #include <rpi_shared.h>
  22
  23 /*
  24  * Fields at the beginning of armstub8.bin.
  25  * While building the BL31 image, we put the stub magic into the binary.
  26  * The GPU firmware detects this at boot time, clears that field as a
  27  * confirmation and puts the kernel and DT address in the following words.
  28  */
  29 extern uint32_t stub_magic;
  30
  31 static const gicv2_driver_data_t rpi4_gic_data = {
  32         .gicd_base = RPI4_GIC_GICD_BASE,
  33         .gicc_base = RPI4_GIC_GICC_BASE,
  34 };
  35
  36 /*
  37  * To be filled by the code below. At the moment BL32 is not supported.
  38  * In the future these might be passed down from BL2.
  39  */
  40 static entry_point_info_t bl32_image_ep_info;
  41 static entry_point_info_t bl33_image_ep_info;
  42
  43 /*******************************************************************************
  44  * Return a pointer to the 'entry_point_info' structure of the next image for
  45  * the security state specified. BL33 corresponds to the non-secure image type
  46  * while BL32 corresponds to the secure image type. A NULL pointer is returned
  47  * if the image does not exist.
  48  ******************************************************************************/
  49 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  50 {
  51         entry_point_info_t *next_image_info;
  52
  53         assert(sec_state_is_valid(type) != 0);
  54
  55         next_image_info = (type == NON_SECURE)
  56                         ? &bl33_image_ep_info : &bl32_image_ep_info;
  57
  58         /* None of the images can have 0x0 as the entrypoint. */
  59         if (next_image_info->pc) {
  60                 return next_image_info;
  61         } else {
  62                 return NULL;
  63         }
  64 }
  65
  66 static void ldelay(register_t delay)
  67 {
  68         __asm__ volatile (
  69                 "1:\tcbz %0, 2f\n\t"
  70                 "sub %0, %0, #1\n\t"
  71                 "b 1b\n"
  72                 "2:"
  73                 : "=&r" (delay) : "0" (delay)
  74         );
  75 }
  76
  77 /*******************************************************************************
  78  * Perform any BL31 early platform setup. Here is an opportunity to copy
  79  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before
  80  * they are lost (potentially). This needs to be done before the MMU is
  81  * initialized so that the memory layout can be used while creating page
  82  * tables. BL2 has flushed this information to memory, so we are guaranteed
  83  * to pick up good data.
  84  ******************************************************************************/
  85 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
  86                                 u_register_t arg2, u_register_t arg3)
  87
  88 {
  89         uint32_t div_reg;
  90
  91         /*
  92          * LOCAL_CONTROL:
  93          * Bit 9 clear: Increment by 1 (vs. 2).
  94          * Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB).
  95          */
  96         mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0);
  97
  98         /* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */
  99         mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000);
 100
 101         /* Early GPU firmware revisions need a little break here. */
 102         ldelay(100000);
 103
 104         /*
 105          * Initialize the console to provide early debug support.
 106          * Different GPU firmware revisions set up the VPU divider differently,
 107          * so read the actual divider register to learn the UART base clock
 108          * rate. The divider is encoded as a 12.12 fixed point number, but we
 109          * just care about the integer part of it.
 110          */
 111         div_reg = mmio_read_32(RPI4_CLOCK_BASE + RPI4_VPU_CLOCK_DIVIDER);
 112         div_reg = (div_reg >> 12) & 0xfff;
 113         if (div_reg == 0)
 114                 div_reg = 1;
 115         rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg);
 116
 117 #if RPI3_DIRECT_LINUX_BOOT
 118         bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
 119         bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
 120                                           DISABLE_ALL_EXCEPTIONS);
 121         SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 122
 123 # if RPI3_BL33_IN_AARCH32
 124         /*
 125          * According to the file ``Documentation/arm/Booting`` of the Linux
 126          * kernel tree, Linux expects:
 127          * r0 = 0
 128          * r1 = machine type number, optional in DT-only platforms (~0 if so)
 129          * r2 = Physical address of the device tree blob
 130          */
 131         VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n");
 132         bl33_image_ep_info.args.arg0 = 0U;
 133         bl33_image_ep_info.args.arg1 = ~0U;
 134         bl33_image_ep_info.args.arg2 = (u_register_t) RPI3_PRELOADED_DTB_BASE;
 135 # else
 136         /*
 137          * According to the file ``Documentation/arm64/booting.txt`` of the
 138          * Linux kernel tree, Linux expects the physical address of the device
 139          * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
 140          * must be 0.
 141          */
 142         VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n");
 143         bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE;
 144         bl33_image_ep_info.args.arg1 = 0ULL;
 145         bl33_image_ep_info.args.arg2 = 0ULL;
 146         bl33_image_ep_info.args.arg3 = 0ULL;
 147 # endif /* RPI3_BL33_IN_AARCH32 */
 148 #endif /* RPI3_DIRECT_LINUX_BOOT */
 149 }
 150
 151 void bl31_plat_arch_setup(void)
 152 {
 153         /*
 154          * Add the first page of memory, which holds the stub magic,
 155          * the kernel and the DT address.
 156          * This is read-only, as the GPU already populated the header,
 157          * we just need to read it.
 158          */
 159         mmap_add_region(0, 0, 4096, MT_MEMORY | MT_RO | MT_SECURE);
 160
 161         rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE,
 162                                BL_CODE_BASE, BL_CODE_END,
 163                                BL_RO_DATA_BASE, BL_RO_DATA_END
 164 #if USE_COHERENT_MEM
 165                                , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
 166 #endif
 167                               );
 168
 169         enable_mmu_el3(0);
 170 }
 171
 172 void bl31_platform_setup(void)
 173 {
 174         /* Configure the interrupt controller */
 175         gicv2_driver_init(&rpi4_gic_data);
 176         gicv2_distif_init();
 177         gicv2_pcpu_distif_init();
 178         gicv2_cpuif_enable();
 179 }