plat/rpi/rpi4/rpi4_bl31_setup.c

   1 /*
   2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8
   9 #include <libfdt.h>
  10
  11 #include <platform_def.h>
  12 #include <common/bl_common.h>
  13 #include <lib/mmio.h>
  14 #include <lib/xlat_tables/xlat_mmu_helpers.h>
  15 #include <lib/xlat_tables/xlat_tables_defs.h>
  16 #include <lib/xlat_tables/xlat_tables_v2.h>
  17 #include <plat/common/platform.h>
  18
  19 #include <drivers/arm/gicv2.h>
  20
  21 #include <rpi_shared.h>
  22
  23 /*
  24  * Fields at the beginning of armstub8.bin.
  25  * While building the BL31 image, we put the stub magic into the binary.
  26  * The GPU firmware detects this at boot time, clears that field as a
  27  * confirmation and puts the kernel and DT address in the following words.
  28  */
  29 extern uint32_t stub_magic;
  30 extern uint32_t dtb_ptr32;
  31 extern uint32_t kernel_entry32;
  32
  33 static const gicv2_driver_data_t rpi4_gic_data = {
  34         .gicd_base = RPI4_GIC_GICD_BASE,
  35         .gicc_base = RPI4_GIC_GICC_BASE,
  36 };
  37
  38 /*
  39  * To be filled by the code below. At the moment BL32 is not supported.
  40  * In the future these might be passed down from BL2.
  41  */
  42 static entry_point_info_t bl32_image_ep_info;
  43 static entry_point_info_t bl33_image_ep_info;
  44
  45 /*******************************************************************************
  46  * Return a pointer to the 'entry_point_info' structure of the next image for
  47  * the security state specified. BL33 corresponds to the non-secure image type
  48  * while BL32 corresponds to the secure image type. A NULL pointer is returned
  49  * if the image does not exist.
  50  ******************************************************************************/
  51 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  52 {
  53         entry_point_info_t *next_image_info;
  54
  55         assert(sec_state_is_valid(type) != 0);
  56
  57         next_image_info = (type == NON_SECURE)
  58                         ? &bl33_image_ep_info : &bl32_image_ep_info;
  59
  60         /* None of the images can have 0x0 as the entrypoint. */
  61         if (next_image_info->pc) {
  62                 return next_image_info;
  63         } else {
  64                 return NULL;
  65         }
  66 }
  67
  68 uintptr_t plat_get_ns_image_entrypoint(void)
  69 {
  70 #ifdef PRELOADED_BL33_BASE
  71         return PRELOADED_BL33_BASE;
  72 #else
  73         /* Cleared by the GPU if kernel address is valid. */
  74         if (stub_magic == 0)
  75                 return kernel_entry32;
  76
  77         WARN("Stub magic failure, using default kernel address 0x80000\n");
  78         return 0x80000;
  79 #endif
  80 }
  81
  82 static uintptr_t rpi4_get_dtb_address(void)
  83 {
  84 #ifdef RPI3_PRELOADED_DTB_BASE
  85         return RPI3_PRELOADED_DTB_BASE;
  86 #else
  87         /* Cleared by the GPU if DTB address is valid. */
  88         if (stub_magic == 0)
  89                 return dtb_ptr32;
  90
  91         WARN("Stub magic failure, DTB address unknown\n");
  92         return 0;
  93 #endif
  94 }
  95
  96 static void ldelay(register_t delay)
  97 {
  98         __asm__ volatile (
  99                 "1:\tcbz %0, 2f\n\t"
 100                 "sub %0, %0, #1\n\t"
 101                 "b 1b\n"
 102                 "2:"
 103                 : "=&r" (delay) : "0" (delay)
 104         );
 105 }
 106
 107 /*******************************************************************************
 108  * Perform any BL31 early platform setup. Here is an opportunity to copy
 109  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before
 110  * they are lost (potentially). This needs to be done before the MMU is
 111  * initialized so that the memory layout can be used while creating page
 112  * tables. BL2 has flushed this information to memory, so we are guaranteed
 113  * to pick up good data.
 114  ******************************************************************************/
 115 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 116                                 u_register_t arg2, u_register_t arg3)
 117
 118 {
 119         uint32_t div_reg;
 120
 121         /*
 122          * LOCAL_CONTROL:
 123          * Bit 9 clear: Increment by 1 (vs. 2).
 124          * Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB).
 125          */
 126         mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0);
 127
 128         /* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */
 129         mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000);
 130
 131         /* Early GPU firmware revisions need a little break here. */
 132         ldelay(100000);
 133
 134         /*
 135          * Initialize the console to provide early debug support.
 136          * Different GPU firmware revisions set up the VPU divider differently,
 137          * so read the actual divider register to learn the UART base clock
 138          * rate. The divider is encoded as a 12.12 fixed point number, but we
 139          * just care about the integer part of it.
 140          */
 141         div_reg = mmio_read_32(RPI4_CLOCK_BASE + RPI4_VPU_CLOCK_DIVIDER);
 142         div_reg = (div_reg >> 12) & 0xfff;
 143         if (div_reg == 0)
 144                 div_reg = 1;
 145         rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg);
 146
 147         bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
 148         bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
 149         SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 150
 151 #if RPI3_DIRECT_LINUX_BOOT
 152 # if RPI3_BL33_IN_AARCH32
 153         /*
 154          * According to the file ``Documentation/arm/Booting`` of the Linux
 155          * kernel tree, Linux expects:
 156          * r0 = 0
 157          * r1 = machine type number, optional in DT-only platforms (~0 if so)
 158          * r2 = Physical address of the device tree blob
 159          */
 160         VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n");
 161         bl33_image_ep_info.args.arg0 = 0U;
 162         bl33_image_ep_info.args.arg1 = ~0U;
 163         bl33_image_ep_info.args.arg2 = rpi4_get_dtb_address();
 164 # else
 165         /*
 166          * According to the file ``Documentation/arm64/booting.txt`` of the
 167          * Linux kernel tree, Linux expects the physical address of the device
 168          * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
 169          * must be 0.
 170          */
 171         VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n");
 172         bl33_image_ep_info.args.arg0 = rpi4_get_dtb_address();
 173         bl33_image_ep_info.args.arg1 = 0ULL;
 174         bl33_image_ep_info.args.arg2 = 0ULL;
 175         bl33_image_ep_info.args.arg3 = 0ULL;
 176 # endif /* RPI3_BL33_IN_AARCH32 */
 177 #endif /* RPI3_DIRECT_LINUX_BOOT */
 178 }
 179
 180 void bl31_plat_arch_setup(void)
 181 {
 182         /*
 183          * Add the first page of memory, which holds the stub magic,
 184          * the kernel and the DT address.
 185          * This is read-only, as the GPU already populated the header,
 186          * we just need to read it.
 187          */
 188         mmap_add_region(0, 0, 4096, MT_MEMORY | MT_RO | MT_SECURE);
 189
 190         rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE,
 191                                BL_CODE_BASE, BL_CODE_END,
 192                                BL_RO_DATA_BASE, BL_RO_DATA_END
 193 #if USE_COHERENT_MEM
 194                                , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
 195 #endif
 196                               );
 197
 198         enable_mmu_el3(0);
 199 }
 200
 201 void bl31_platform_setup(void)
 202 {
 203         /* Configure the interrupt controller */
 204         gicv2_driver_init(&rpi4_gic_data);
 205         gicv2_distif_init();
 206         gicv2_pcpu_distif_init();
 207         gicv2_cpuif_enable();
 208 }