plat/rpi3/rpi3_common.c

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch_helpers.h>
   8 #include <assert.h>
   9 #include <bl_common.h>
  10 #include <console.h>
  11 #include <debug.h>
  12 #include <interrupt_mgmt.h>
  13 #include <platform_def.h>
  14 #include <uart_16550.h>
  15 #include <xlat_tables_v2.h>
  16
  17 #include "rpi3_hw.h"
  18 #include "rpi3_private.h"
  19
  20 #define MAP_DEVICE0     MAP_REGION_FLAT(DEVICE0_BASE,                   \
  21                                         DEVICE0_SIZE,                   \
  22                                         MT_DEVICE | MT_RW | MT_SECURE)
  23
  24 #define MAP_SHARED_RAM  MAP_REGION_FLAT(SHARED_RAM_BASE,                \
  25                                         SHARED_RAM_SIZE,                \
  26                                         MT_DEVICE | MT_RW | MT_SECURE)
  27
  28 #ifdef RPI3_PRELOADED_DTB_BASE
  29 #define MAP_NS_DTB      MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \
  30                                         MT_MEMORY | MT_RW | MT_NS)
  31 #endif
  32
  33 #define MAP_NS_DRAM0    MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE,   \
  34                                         MT_MEMORY | MT_RW | MT_NS)
  35
  36 #define MAP_FIP         MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE,             \
  37                                         PLAT_RPI3_FIP_MAX_SIZE,         \
  38                                         MT_MEMORY | MT_RO | MT_NS)
  39
  40 #define MAP_BL32_MEM    MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE,   \
  41                                         MT_MEMORY | MT_RW | MT_SECURE)
  42
  43 #ifdef SPD_opteed
  44 #define MAP_OPTEE_PAGEABLE      MAP_REGION_FLAT(                \
  45                                 RPI3_OPTEE_PAGEABLE_LOAD_BASE,  \
  46                                 RPI3_OPTEE_PAGEABLE_LOAD_SIZE,  \
  47                                 MT_MEMORY | MT_RW | MT_SECURE)
  48 #endif
  49
  50 /*
  51  * Table of regions for various BL stages to map using the MMU.
  52  */
  53 #ifdef IMAGE_BL1
  54 static const mmap_region_t plat_rpi3_mmap[] = {
  55         MAP_SHARED_RAM,
  56         MAP_DEVICE0,
  57         MAP_FIP,
  58 #ifdef SPD_opteed
  59         MAP_OPTEE_PAGEABLE,
  60 #endif
  61         {0}
  62 };
  63 #endif
  64
  65 #ifdef IMAGE_BL2
  66 static const mmap_region_t plat_rpi3_mmap[] = {
  67         MAP_SHARED_RAM,
  68         MAP_DEVICE0,
  69         MAP_FIP,
  70         MAP_NS_DRAM0,
  71 #ifdef BL32_BASE
  72         MAP_BL32_MEM,
  73 #endif
  74         {0}
  75 };
  76 #endif
  77
  78 #ifdef IMAGE_BL31
  79 static const mmap_region_t plat_rpi3_mmap[] = {
  80         MAP_SHARED_RAM,
  81         MAP_DEVICE0,
  82 #ifdef RPI3_PRELOADED_DTB_BASE
  83         MAP_NS_DTB,
  84 #endif
  85 #ifdef BL32_BASE
  86         MAP_BL32_MEM,
  87 #endif
  88         {0}
  89 };
  90 #endif
  91
  92 /*******************************************************************************
  93  * Function that sets up the console
  94  ******************************************************************************/
  95 static console_16550_t rpi3_console;
  96
  97 void rpi3_console_init(void)
  98 {
  99         int console_scope = CONSOLE_FLAG_BOOT;
 100 #if RPI3_RUNTIME_UART != -1
 101         console_scope |= CONSOLE_FLAG_RUNTIME;
 102 #endif
 103         int rc = console_16550_register(PLAT_RPI3_UART_BASE,
 104                                         PLAT_RPI3_UART_CLK_IN_HZ,
 105                                         PLAT_RPI3_UART_BAUDRATE,
 106                                         &rpi3_console);
 107         if (rc == 0) {
 108                 /*
 109                  * The crash console doesn't use the multi console API, it uses
 110                  * the core console functions directly. It is safe to call panic
 111                  * and let it print debug information.
 112                  */
 113                 panic();
 114         }
 115
 116         console_set_scope(&rpi3_console.console, console_scope);
 117 }
 118
 119 /*******************************************************************************
 120  * Function that sets up the translation tables.
 121  ******************************************************************************/
 122 void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
 123                             uintptr_t code_start, uintptr_t code_limit,
 124                             uintptr_t rodata_start, uintptr_t rodata_limit
 125 #if USE_COHERENT_MEM
 126                             , uintptr_t coh_start, uintptr_t coh_limit
 127 #endif
 128                             )
 129 {
 130         /*
 131          * Map the Trusted SRAM with appropriate memory attributes.
 132          * Subsequent mappings will adjust the attributes for specific regions.
 133          */
 134         VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
 135                 (void *) total_base, (void *) (total_base + total_size));
 136         mmap_add_region(total_base, total_base,
 137                         total_size,
 138                         MT_MEMORY | MT_RW | MT_SECURE);
 139
 140         /* Re-map the code section */
 141         VERBOSE("Code region: %p - %p\n",
 142                 (void *) code_start, (void *) code_limit);
 143         mmap_add_region(code_start, code_start,
 144                         code_limit - code_start,
 145                         MT_CODE | MT_SECURE);
 146
 147         /* Re-map the read-only data section */
 148         VERBOSE("Read-only data region: %p - %p\n",
 149                 (void *) rodata_start, (void *) rodata_limit);
 150         mmap_add_region(rodata_start, rodata_start,
 151                         rodata_limit - rodata_start,
 152                         MT_RO_DATA | MT_SECURE);
 153
 154 #if USE_COHERENT_MEM
 155         /* Re-map the coherent memory region */
 156         VERBOSE("Coherent region: %p - %p\n",
 157                 (void *) coh_start, (void *) coh_limit);
 158         mmap_add_region(coh_start, coh_start,
 159                         coh_limit - coh_start,
 160                         MT_DEVICE | MT_RW | MT_SECURE);
 161 #endif
 162
 163         mmap_add(plat_rpi3_mmap);
 164
 165         init_xlat_tables();
 166 }
 167
 168 /*******************************************************************************
 169  * Return entrypoint of BL33.
 170  ******************************************************************************/
 171 uintptr_t plat_get_ns_image_entrypoint(void)
 172 {
 173 #ifdef PRELOADED_BL33_BASE
 174         return PRELOADED_BL33_BASE;
 175 #else
 176         return PLAT_RPI3_NS_IMAGE_OFFSET;
 177 #endif
 178 }
 179
 180 /*******************************************************************************
 181  * Gets SPSR for BL32 entry
 182  ******************************************************************************/
 183 uint32_t rpi3_get_spsr_for_bl32_entry(void)
 184 {
 185         /*
 186          * The Secure Payload Dispatcher service is responsible for
 187          * setting the SPSR prior to entry into the BL32 image.
 188          */
 189         return 0;
 190 }
 191
 192 /*******************************************************************************
 193  * Gets SPSR for BL33 entry
 194  ******************************************************************************/
 195 uint32_t rpi3_get_spsr_for_bl33_entry(void)
 196 {
 197 #if RPI3_BL33_IN_AARCH32
 198         INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n");
 199         return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE,
 200                            DISABLE_ALL_EXCEPTIONS);
 201 #else
 202         return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
 203 #endif
 204 }
 205
 206 unsigned int plat_get_syscnt_freq2(void)
 207 {
 208         return SYS_COUNTER_FREQ_IN_TICKS;
 209 }
 210
 211 uint32_t plat_ic_get_pending_interrupt_type(void)
 212 {
 213         ERROR("rpi3: Interrupt routed to EL3.\n");
 214         return INTR_TYPE_INVAL;
 215 }
 216
 217 uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
 218 {
 219         assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) ||
 220                (type == INTR_TYPE_NS));
 221
 222         assert(sec_state_is_valid(security_state));
 223
 224         /* Non-secure interrupts are signalled on the IRQ line always. */
 225         if (type == INTR_TYPE_NS)
 226                 return __builtin_ctz(SCR_IRQ_BIT);
 227
 228         /* Secure interrupts are signalled on the FIQ line always. */
 229         return  __builtin_ctz(SCR_FIQ_BIT);
 230 }