plat/socionext/uniphier/uniphier_bl31_setup.c

   1 /*
   2  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch.h>
   8 #include <assert.h>
   9 #include <bl_common.h>
  10 #include <console.h>
  11 #include <debug.h>
  12 #include <errno.h>
  13 #include <mmio.h>
  14 #include <platform.h>
  15 #include <platform_def.h>
  16 #include <xlat_mmu_helpers.h>
  17
  18 #include "uniphier.h"
  19
  20 #define BL31_SIZE               ((BL31_END) - (BL31_BASE))
  21
  22 static entry_point_info_t bl32_image_ep_info;
  23 static entry_point_info_t bl33_image_ep_info;
  24
  25 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  26 {
  27         assert(sec_state_is_valid(type));
  28         return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info;
  29 }
  30
  31 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
  32                                 u_register_t arg2, u_register_t arg3)
  33 {
  34         void *from_bl2;
  35
  36         from_bl2 = (void *) arg0;
  37
  38         bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
  39
  40         uniphier_console_setup();
  41
  42         while (bl_params) {
  43                 if (bl_params->image_id == BL32_IMAGE_ID)
  44                         bl32_image_ep_info = *bl_params->ep_info;
  45
  46                 if (bl_params->image_id == BL33_IMAGE_ID)
  47                         bl33_image_ep_info = *bl_params->ep_info;
  48
  49                 bl_params = bl_params->next_params_info;
  50         }
  51
  52         if (bl33_image_ep_info.pc == 0)
  53                 panic();
  54 }
  55
  56 #define UNIPHIER_SYS_CNTCTL_BASE        0x60E00000
  57
  58 void bl31_platform_setup(void)
  59 {
  60         unsigned int soc;
  61
  62         soc = uniphier_get_soc_id();
  63         if (soc == UNIPHIER_SOC_UNKNOWN) {
  64                 ERROR("unsupported SoC\n");
  65                 plat_error_handler(-ENOTSUP);
  66         }
  67
  68         uniphier_cci_init(soc);
  69         uniphier_cci_enable();
  70
  71         /* Initialize the GIC driver, cpu and distributor interfaces */
  72         uniphier_gic_driver_init(soc);
  73         uniphier_gic_init();
  74
  75         /* Enable and initialize the System level generic timer */
  76         mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
  77                         CNTCR_FCREQ(0U) | CNTCR_EN);
  78 }
  79
  80 void bl31_plat_arch_setup(void)
  81 {
  82         uniphier_mmap_setup(BL31_BASE, BL31_SIZE, NULL);
  83         enable_mmu_el3(0);
  84 }
  85
  86 void bl31_plat_runtime_setup(void)
  87 {
  88         /* Suppress any runtime logs unless DEBUG is defined */
  89 #if !DEBUG
  90         console_uninit();
  91 #endif
  92 }