plat/st/common/include/stm32mp_common.h

   1 /*
   2  * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
   3  * Copyright (c) 2018-2019, Linaro Limited
   4  *
   5  * SPDX-License-Identifier: BSD-3-Clause
   6  */
   7
   8 #ifndef STM32MP_COMMON_H
   9 #define STM32MP_COMMON_H
  10
  11 #include <stdbool.h>
  12
  13 #include <platform_def.h>
  14
  15 #include <arch_helpers.h>
  16
  17 /* Functions to save and get boot context address given by ROM code */
  18 void stm32mp_save_boot_ctx_address(uintptr_t address);
  19 uintptr_t stm32mp_get_boot_ctx_address(void);
  20
  21 bool stm32mp_is_single_core(void);
  22 bool stm32mp_is_closed_device(void);
  23
  24 /* Return the base address of the DDR controller */
  25 uintptr_t stm32mp_ddrctrl_base(void);
  26
  27 /* Return the base address of the DDR PHY */
  28 uintptr_t stm32mp_ddrphyc_base(void);
  29
  30 /* Return the base address of the PWR peripheral */
  31 uintptr_t stm32mp_pwr_base(void);
  32
  33 /* Return the base address of the RCC peripheral */
  34 uintptr_t stm32mp_rcc_base(void);
  35
  36 /* Check MMU status to allow spinlock use */
  37 bool stm32mp_lock_available(void);
  38
  39 /* Get IWDG platform instance ID from peripheral IO memory base address */
  40 uint32_t stm32_iwdg_get_instance(uintptr_t base);
  41
  42 /* Return bitflag mask for expected IWDG configuration from OTP content */
  43 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst);
  44
  45 #if defined(IMAGE_BL2)
  46 /* Update OTP shadow registers with IWDG configuration from device tree */
  47 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags);
  48 #endif
  49
  50 /*
  51  * Platform util functions for the GPIO driver
  52  * @bank: Target GPIO bank ID as per DT bindings
  53  *
  54  * Platform shall implement these functions to provide to stm32_gpio
  55  * driver the resource reference for a target GPIO bank. That are
  56  * memory mapped interface base address, interface offset (see below)
  57  * and clock identifier.
  58  *
  59  * stm32_get_gpio_bank_offset() returns a bank offset that is used to
  60  * check DT configuration matches platform implementation of the banks
  61  * description.
  62  */
  63 uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
  64 unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
  65 uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
  66
  67 /* Print CPU information */
  68 void stm32mp_print_cpuinfo(void);
  69
  70 /* Print board information */
  71 void stm32mp_print_boardinfo(void);
  72
  73 /*
  74  * Util for clock gating and to get clock rate for stm32 and platform drivers
  75  * @id: Target clock ID, ID used in clock DT bindings
  76  */
  77 bool stm32mp_clk_is_enabled(unsigned long id);
  78 void stm32mp_clk_enable(unsigned long id);
  79 void stm32mp_clk_disable(unsigned long id);
  80 unsigned long stm32mp_clk_get_rate(unsigned long id);
  81
  82 /* Initialise the IO layer and register platform IO devices */
  83 void stm32mp_io_setup(void);
  84
  85 static inline uint64_t arm_cnt_us2cnt(uint32_t us)
  86 {
  87         return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL;
  88 }
  89
  90 static inline uint64_t timeout_init_us(uint32_t us)
  91 {
  92         return read_cntpct_el0() + arm_cnt_us2cnt(us);
  93 }
  94
  95 static inline bool timeout_elapsed(uint64_t expire)
  96 {
  97         return read_cntpct_el0() > expire;
  98 }
  99
 100 /*
 101  * Check that the STM32 header of a .stm32 binary image is valid
 102  * @param header: pointer to the stm32 image header
 103  * @param buffer: address of the binary image (payload)
 104  * @return: 0 on success, negative value in case of error
 105  */
 106 int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer);
 107
 108 #endif /* STM32MP_COMMON_H */