plat/xilinx/versal/include/plat_macros.S

   1 /*
   2  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef PLAT_MACROS_S
   8 #define PLAT_MACROS_S
   9
  10 #include "../include/platform_def.h"
  11 #include <gic_common.h>
  12 #include <gicv2.h>
  13 #include <gicv3.h>
  14
  15 .section .rodata.gic_reg_name, "aS"
  16 /* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
  17 gicc_regs:
  18         .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
  19
  20 /* Applicable only to GICv3 with SRE enabled */
  21 icc_regs:
  22         .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
  23
  24 /* Registers common to both GICv2 and GICv3 */
  25 gicd_pend_reg:
  26         .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
  27 newline:
  28         .asciz "\n"
  29 spacer:
  30         .asciz ":\t\t0x"
  31
  32         /* ---------------------------------------------
  33          * The below utility macro prints out relevant GIC
  34          * registers whenever an unhandled exception is
  35          * taken in BL31 on Versal platform.
  36          * Expects: GICD base in x16, GICC base in x17
  37          * Clobbers: x0 - x10, sp
  38          * ---------------------------------------------
  39          */
  40         .macro versal_print_gic_regs
  41         /* Check for GICv3 system register access */
  42         mrs     x7, id_aa64pfr0_el1
  43         ubfx    x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
  44         cmp     x7, #1
  45         b.ne    print_gicv2
  46
  47         /* Check for SRE enable */
  48         mrs     x8, ICC_SRE_EL3
  49         tst     x8, #ICC_SRE_SRE_BIT
  50         b.eq    print_gicv2
  51
  52         /* Load the icc reg list to x6 */
  53         adr     x6, icc_regs
  54         /* Load the icc regs to gp regs used by str_in_crash_buf_print */
  55         mrs     x8, ICC_HPPIR0_EL1
  56         mrs     x9, ICC_HPPIR1_EL1
  57         mrs     x10, ICC_CTLR_EL3
  58         /* Store to the crash buf and print to console */
  59         bl      str_in_crash_buf_print
  60         b       print_gic_common
  61
  62 print_gicv2:
  63         /* Load the gicc reg list to x6 */
  64         adr     x6, gicc_regs
  65         /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
  66         ldr     w8, [x17, #GICC_HPPIR]
  67         ldr     w9, [x17, #GICC_AHPPIR]
  68         ldr     w10, [x17, #GICC_CTLR]
  69         /* Store to the crash buf and print to console */
  70         bl      str_in_crash_buf_print
  71
  72 print_gic_common:
  73         /* Print the GICD_ISPENDR regs */
  74         add     x7, x16, #GICD_ISPENDR
  75         adr     x4, gicd_pend_reg
  76         bl      asm_print_str
  77 gicd_ispendr_loop:
  78         sub     x4, x7, x16
  79         cmp     x4, #0x280
  80         b.eq    exit_print_gic_regs
  81         bl      asm_print_hex
  82
  83         adr     x4, spacer
  84         bl      asm_print_str
  85
  86         ldr     x4, [x7], #8
  87         bl      asm_print_hex
  88
  89         adr     x4, newline
  90         bl      asm_print_str
  91         b       gicd_ispendr_loop
  92 exit_print_gic_regs:
  93         .endm
  94
  95         /* ---------------------------------------------
  96          * The below required platform porting macro
  97          * prints out relevant GIC and CCI registers
  98          * whenever an unhandled exception is taken in
  99          * BL31.
 100          * Clobbers: x0 - x10, x16, x17, sp
 101          * ---------------------------------------------
 102          */
 103         .macro plat_crash_print_regs
 104         mov_imm x17, PLAT_VERSAL_GICD_BASE
 105         mov_imm x16, PLAT_VERSAL_GICR_BASE
 106         versal_print_gic_regs
 107         .endm
 108
 109 #endif /* PLAT_MACROS_S */