plat/xilinx/zynqmp/bl31_zynqmp_setup.c

   1 /*
   2  * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8 #include <bl31.h>
   9 #include <bl_common.h>
  10 #include <console.h>
  11 #include <debug.h>
  12 #include <errno.h>
  13 #include <plat_arm.h>
  14 #include <platform.h>
  15 #include "zynqmp_private.h"
  16
  17 #define BL31_END (unsigned long)(&__BL31_END__)
  18
  19 static entry_point_info_t bl32_image_ep_info;
  20 static entry_point_info_t bl33_image_ep_info;
  21
  22 /*
  23  * Return a pointer to the 'entry_point_info' structure of the next image for
  24  * the security state specified. BL33 corresponds to the non-secure image type
  25  * while BL32 corresponds to the secure image type. A NULL pointer is returned
  26  * if the image does not exist.
  27  */
  28 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  29 {
  30         assert(sec_state_is_valid(type));
  31
  32         if (type == NON_SECURE)
  33                 return &bl33_image_ep_info;
  34
  35         return &bl32_image_ep_info;
  36 }
  37
  38 /*
  39  * Set the build time defaults. We want to do this when doing a JTAG boot
  40  * or if we can't find any other config data.
  41  */
  42 static inline void bl31_set_default_config(void)
  43 {
  44         bl32_image_ep_info.pc = BL32_BASE;
  45         bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
  46         bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
  47         bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
  48                                           DISABLE_ALL_EXCEPTIONS);
  49 }
  50
  51 /*
  52  * Perform any BL31 specific platform actions. Here is an opportunity to copy
  53  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
  54  * are lost (potentially). This needs to be done before the MMU is initialized
  55  * so that the memory layout can be used while creating page tables.
  56  */
  57 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
  58                                 u_register_t arg2, u_register_t arg3)
  59 {
  60         /* Initialize the console to provide early debug support */
  61         console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(),
  62                      ZYNQMP_UART_BAUDRATE);
  63
  64         /* Initialize the platform config for future decision making */
  65         zynqmp_config_setup();
  66
  67         /* There are no parameters from BL2 if BL31 is a reset vector */
  68         assert(arg0 == 0U);
  69         assert(arg1 == 0U);
  70
  71         /*
  72          * Do initial security configuration to allow DRAM/device access. On
  73          * Base ZYNQMP only DRAM security is programmable (via TrustZone), but
  74          * other platforms might have more programmable security devices
  75          * present.
  76          */
  77
  78         /* Populate common information for BL32 and BL33 */
  79         SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
  80         SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
  81         SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
  82         SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
  83
  84         if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
  85                 bl31_set_default_config();
  86         } else {
  87                 /* use parameters from FSBL */
  88                 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
  89                                                           &bl33_image_ep_info);
  90                 if (ret == FSBL_HANDOFF_NO_STRUCT)
  91                         bl31_set_default_config();
  92                 else if (ret != FSBL_HANDOFF_SUCCESS)
  93                         panic();
  94         }
  95
  96         NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
  97         NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
  98 }
  99
 100 /* Enable the test setup */
 101 #ifndef ZYNQMP_TESTING
 102 static void zynqmp_testing_setup(void) { }
 103 #else
 104 static void zynqmp_testing_setup(void)
 105 {
 106         uint32_t actlr_el3, actlr_el2;
 107
 108         /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */
 109         actlr_el3 = read_actlr_el3();
 110         actlr_el2 = read_actlr_el2();
 111
 112         actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
 113         actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
 114         write_actlr_el3(actlr_el3);
 115         write_actlr_el2(actlr_el2);
 116 }
 117 #endif
 118
 119 #if ZYNQMP_WDT_RESTART
 120 static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3];
 121
 122 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
 123 {
 124         /* Validate 'handler' and 'id' parameters */
 125         if (!handler || id >= MAX_INTR_EL3)
 126                 return -EINVAL;
 127
 128         /* Check if a handler has already been registered */
 129         if (type_el3_interrupt_table[id])
 130                 return -EALREADY;
 131
 132         type_el3_interrupt_table[id] = handler;
 133
 134         return 0;
 135 }
 136
 137 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
 138                                           void *handle, void *cookie)
 139 {
 140         uint32_t intr_id;
 141         interrupt_type_handler_t handler;
 142
 143         intr_id = plat_ic_get_pending_interrupt_id();
 144         handler = type_el3_interrupt_table[intr_id];
 145         if (handler != NULL)
 146                 handler(intr_id, flags, handle, cookie);
 147
 148         return 0;
 149 }
 150 #endif
 151
 152 void bl31_platform_setup(void)
 153 {
 154         /* Initialize the gic cpu and distributor interfaces */
 155         plat_arm_gic_driver_init();
 156         plat_arm_gic_init();
 157         zynqmp_testing_setup();
 158 }
 159
 160 void bl31_plat_runtime_setup(void)
 161 {
 162 #if ZYNQMP_WDT_RESTART
 163         uint64_t flags = 0;
 164         uint64_t rc;
 165
 166         set_interrupt_rm_flag(flags, NON_SECURE);
 167         rc = register_interrupt_type_handler(INTR_TYPE_EL3,
 168                                              rdo_el3_interrupt_handler, flags);
 169         if (rc)
 170                 panic();
 171 #endif
 172 }
 173
 174 /*
 175  * Perform the very early platform specific architectural setup here.
 176  */
 177 void bl31_plat_arch_setup(void)
 178 {
 179         plat_arm_interconnect_init();
 180         plat_arm_interconnect_enter_coherency();
 181
 182
 183         const mmap_region_t bl_regions[] = {
 184                 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
 185                         MT_MEMORY | MT_RW | MT_SECURE),
 186                 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
 187                                 MT_CODE | MT_SECURE),
 188                 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
 189                                 MT_RO_DATA | MT_SECURE),
 190                 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
 191                                 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
 192                                 MT_DEVICE | MT_RW | MT_SECURE),
 193                 {0}
 194         };
 195
 196         setup_page_tables(bl_regions, plat_arm_get_mmap());
 197         enable_mmu_el3(0);
 198 }