target/linux/adm5120/files/arch/mips/adm5120/irq.c

   1 /*
   2  *  ADM5120 specific interrupt handlers
   3  *
   4  *  Copyright (C) 2007-2008 OpenWrt.org
   5  *  Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  *
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/version.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/ioport.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/irq.h>
  21 #include <asm/irq_cpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/bitops.h>
  24
  25 #include <asm/mach-adm5120/adm5120_defs.h>
  26 #include <asm/mach-adm5120/adm5120_irq.h>
  27
  28 static void adm5120_intc_irq_unmask(unsigned int irq);
  29 static void adm5120_intc_irq_mask(unsigned int irq);
  30 static int  adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type);
  31
  32 static inline void intc_write_reg(unsigned int reg, u32 val)
  33 {
  34         void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
  35
  36         __raw_writel(val, base + reg);
  37 }
  38
  39 static inline u32 intc_read_reg(unsigned int reg)
  40 {
  41         void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
  42
  43         return __raw_readl(base + reg);
  44 }
  45
  46 static struct irq_chip adm5120_intc_irq_chip = {
  47         .name           = "INTC",
  48         .unmask         = adm5120_intc_irq_unmask,
  49         .mask           = adm5120_intc_irq_mask,
  50         .mask_ack       = adm5120_intc_irq_mask,
  51         .set_type       = adm5120_intc_irq_set_type
  52 };
  53
  54 static struct irqaction adm5120_intc_irq_action = {
  55         .handler        = no_action,
  56         .name           = "cascade [INTC]"
  57 };
  58
  59 static void adm5120_intc_irq_unmask(unsigned int irq)
  60 {
  61         irq -= ADM5120_INTC_IRQ_BASE;
  62         intc_write_reg(INTC_REG_IRQ_ENABLE, 1 << irq);
  63 }
  64
  65 static void adm5120_intc_irq_mask(unsigned int irq)
  66 {
  67         irq -= ADM5120_INTC_IRQ_BASE;
  68         intc_write_reg(INTC_REG_IRQ_DISABLE, 1 << irq);
  69 }
  70
  71 static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type)
  72 {
  73         unsigned int sense;
  74         unsigned long mode;
  75         int err = 0;
  76
  77         sense = flow_type & (IRQ_TYPE_SENSE_MASK);
  78         switch (sense) {
  79         case IRQ_TYPE_NONE:
  80         case IRQ_TYPE_LEVEL_HIGH:
  81                 break;
  82         case IRQ_TYPE_LEVEL_LOW:
  83                 switch (irq) {
  84                 case ADM5120_IRQ_GPIO2:
  85                 case ADM5120_IRQ_GPIO4:
  86                         break;
  87                 default:
  88                         err = -EINVAL;
  89                         break;
  90                 }
  91                 break;
  92         default:
  93                 err = -EINVAL;
  94                 break;
  95         }
  96
  97         if (err)
  98                 return err;
  99
 100         switch (irq) {
 101         case ADM5120_IRQ_GPIO2:
 102         case ADM5120_IRQ_GPIO4:
 103                 mode = intc_read_reg(INTC_REG_INT_MODE);
 104                 if (sense == IRQ_TYPE_LEVEL_LOW)
 105                         mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE));
 106                 else
 107                         mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE));
 108
 109                 intc_write_reg(INTC_REG_INT_MODE, mode);
 110                 /* fallthrough */
 111         default:
 112                 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
 113                 irq_desc[irq].status |= sense;
 114                 break;
 115         }
 116
 117         return 0;
 118 }
 119
 120 static void adm5120_intc_irq_dispatch(void)
 121 {
 122         unsigned long status;
 123         int irq;
 124
 125         /* dispatch only one IRQ at a time */
 126         status = intc_read_reg(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
 127
 128         if (status) {
 129                 irq = ADM5120_INTC_IRQ_BASE + fls(status) - 1;
 130                 do_IRQ(irq);
 131         } else
 132                 spurious_interrupt();
 133 }
 134
 135 asmlinkage void plat_irq_dispatch(void)
 136 {
 137         unsigned long pending;
 138
 139         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 140
 141         if (pending & STATUSF_IP7)
 142                 do_IRQ(ADM5120_IRQ_COUNTER);
 143         else if (pending & STATUSF_IP2)
 144                 adm5120_intc_irq_dispatch();
 145         else
 146                 spurious_interrupt();
 147 }
 148
 149 #define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
 150
 151 static void __init adm5120_intc_irq_init(void)
 152 {
 153         int i;
 154
 155         /* disable all interrupts */
 156         intc_write_reg(INTC_REG_IRQ_DISABLE, INTC_INT_ALL);
 157
 158         /* setup all interrupts to generate IRQ instead of FIQ */
 159         intc_write_reg(INTC_REG_INT_MODE, 0);
 160
 161         /* set active level for all external interrupts to HIGH */
 162         intc_write_reg(INTC_REG_INT_LEVEL, 0);
 163
 164         /* disable usage of the TEST_SOURCE register */
 165         intc_write_reg(INTC_REG_IRQ_SOURCE_SELECT, 0);
 166
 167         for (i = ADM5120_INTC_IRQ_BASE;
 168                 i <= ADM5120_INTC_IRQ_BASE + INTC_IRQ_LAST;
 169                 i++) {
 170                 irq_desc[i].status = INTC_IRQ_STATUS;
 171                 set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
 172                         handle_level_irq);
 173         }
 174
 175         setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
 176 }
 177
 178 void __init arch_init_irq(void) {
 179         mips_cpu_irq_init();
 180         adm5120_intc_irq_init();
 181 }