2 * ADM5120 built in ethernet switch driver
4 * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
6 * Inspiration for this driver came from the original ADMtek 2.4
7 * driver, Copyright ADMtek Inc.
9 * NAPI extensions by Thomas Langer (Thomas.Langer@infineon.com)
10 * and Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007
12 * TODO: Add support of high prio queues (currently disabled)
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/errno.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/spinlock.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
27 #include <linux/irq.h>
29 #include <asm/mipsregs.h>
31 #include <adm5120_info.h>
32 #include <adm5120_defs.h>
33 #include <adm5120_irq.h>
34 #include <adm5120_switch.h>
36 #include "adm5120sw.h"
38 #define DRV_NAME "adm5120-switch"
39 #define DRV_DESC "ADM5120 built-in ethernet switch driver"
40 #define DRV_VERSION "0.1.0"
42 MODULE_AUTHOR("Jeroen Vreeken (pe1rxq@amsat.org)");
43 MODULE_DESCRIPTION("ADM5120 ethernet switch driver");
44 MODULE_LICENSE("GPL");
46 /* ------------------------------------------------------------------------ */
48 #if 0 /*def ADM5120_SWITCH_DEBUG*/
49 #define SW_DBG(f, a...) printk(KERN_DEBUG "%s: " f, DRV_NAME , ## a)
51 #define SW_DBG(f, a...) do {} while (0)
53 #define SW_ERR(f, a...) printk(KERN_ERR "%s: " f, DRV_NAME , ## a)
54 #define SW_INFO(f, a...) printk(KERN_INFO "%s: " f, DRV_NAME , ## a)
56 #define SWITCH_NUM_PORTS 6
57 #define ETH_CSUM_LEN 4
59 #define RX_MAX_PKTLEN 1550
60 #define RX_RING_SIZE 64
62 #define TX_RING_SIZE 32
63 #define TX_QUEUE_LEN 28 /* Limit ring entries actually used. */
64 #define TX_TIMEOUT HZ*400
66 #define RX_DESCS_SIZE (RX_RING_SIZE * sizeof(struct dma_desc *))
67 #define RX_SKBS_SIZE (RX_RING_SIZE * sizeof(struct sk_buff *))
68 #define TX_DESCS_SIZE (TX_RING_SIZE * sizeof(struct dma_desc *))
69 #define TX_SKBS_SIZE (TX_RING_SIZE * sizeof(struct sk_buff *))
71 #define SKB_ALLOC_LEN (RX_MAX_PKTLEN + 32)
72 #define SKB_RESERVE_LEN (NET_IP_ALIGN + NET_SKB_PAD)
74 #define SWITCH_INTS_HIGH (SWITCH_INT_SHD | SWITCH_INT_RHD | SWITCH_INT_HDF)
75 #define SWITCH_INTS_LOW (SWITCH_INT_SLD | SWITCH_INT_RLD | SWITCH_INT_LDF)
76 #define SWITCH_INTS_ERR (SWITCH_INT_RDE | SWITCH_INT_SDE | SWITCH_INT_CPUH)
77 #define SWITCH_INTS_Q (SWITCH_INT_P0QF | SWITCH_INT_P1QF | SWITCH_INT_P2QF | \
78 SWITCH_INT_P3QF | SWITCH_INT_P4QF | SWITCH_INT_P5QF | \
79 SWITCH_INT_CPQF | SWITCH_INT_GQF)
81 #define SWITCH_INTS_ALL (SWITCH_INTS_HIGH | SWITCH_INTS_LOW | \
82 SWITCH_INTS_ERR | SWITCH_INTS_Q | \
83 SWITCH_INT_MD | SWITCH_INT_PSC)
85 #define SWITCH_INTS_USED (SWITCH_INTS_LOW | SWITCH_INT_PSC)
86 #define SWITCH_INTS_POLL (SWITCH_INT_RLD | SWITCH_INT_LDF)
88 /* ------------------------------------------------------------------------ */
92 #define DESC_OWN (1UL << 31) /* Owned by the switch */
93 #define DESC_EOR (1UL << 28) /* End of Ring */
94 #define DESC_ADDR_MASK 0x1FFFFFF
95 #define DESC_ADDR(x) ((__u32)(x) & DESC_ADDR_MASK)
97 #define DESC_BUF2_EN (1UL << 31) /* Buffer 2 enable */
100 /* definitions for tx/rx descriptors */
101 #define DESC_PKTLEN_SHIFT 16
102 #define DESC_PKTLEN_MASK 0x7FF
103 /* tx descriptor specific part */
104 #define DESC_CSUM (1UL << 31) /* Append checksum */
105 #define DESC_DSTPORT_SHIFT 8
106 #define DESC_DSTPORT_MASK 0x3F
107 #define DESC_VLAN_MASK 0x3F
108 /* rx descriptor specific part */
109 #define DESC_SRCPORT_SHIFT 12
110 #define DESC_SRCPORT_MASK 0x7
111 #define DESC_DA_MASK 0x3
112 #define DESC_DA_SHIFT 4
113 #define DESC_IPCSUM_FAIL (1UL << 3) /* IP checksum fail */
114 #define DESC_VLAN_TAG (1UL << 2) /* VLAN tag present */
115 #define DESC_TYPE_MASK 0x3 /* mask for Packet type */
116 #define DESC_TYPE_IP 0x0 /* IP packet */
117 #define DESC_TYPE_PPPoE 0x1 /* PPPoE packet */
118 } __attribute__ ((aligned(16)));
120 static inline u32
desc_get_srcport(struct dma_desc
*desc
)
122 return (desc
->misc
>> DESC_SRCPORT_SHIFT
) & DESC_SRCPORT_MASK
;
125 static inline u32
desc_get_pktlen(struct dma_desc
*desc
)
127 return (desc
->misc
>> DESC_PKTLEN_SHIFT
) & DESC_PKTLEN_MASK
;
130 static inline int desc_ipcsum_fail(struct dma_desc
*desc
)
132 return ((desc
->misc
& DESC_IPCSUM_FAIL
) != 0);
135 /* ------------------------------------------------------------------------ */
137 /* default settings - unlimited TX and RX on all ports, default shaper mode */
138 static unsigned char bw_matrix
[SWITCH_NUM_PORTS
] = {
142 static int adm5120_nrdevs
;
144 static struct net_device
*adm5120_devs
[SWITCH_NUM_PORTS
];
145 /* Lookup table port -> device */
146 static struct net_device
*adm5120_port
[SWITCH_NUM_PORTS
];
148 static struct dma_desc
*txl_descs
;
149 static struct dma_desc
*rxl_descs
;
151 static dma_addr_t txl_descs_dma
;
152 static dma_addr_t rxl_descs_dma
;
154 static struct sk_buff
**txl_skbuff
;
155 static struct sk_buff
**rxl_skbuff
;
157 static unsigned int cur_rxl
, dirty_rxl
; /* producer/consumer ring indices */
158 static unsigned int cur_txl
, dirty_txl
;
160 static unsigned int sw_used
;
162 static spinlock_t sw_lock
= SPIN_LOCK_UNLOCKED
;
163 static spinlock_t poll_lock
= SPIN_LOCK_UNLOCKED
;
165 static struct net_device sw_dev
;
167 /* ------------------------------------------------------------------------ */
169 static inline u32
sw_read_reg(u32 reg
)
171 return __raw_readl((void __iomem
*)KSEG1ADDR(ADM5120_SWITCH_BASE
)+reg
);
174 static inline void sw_write_reg(u32 reg
, u32 val
)
176 __raw_writel(val
, (void __iomem
*)KSEG1ADDR(ADM5120_SWITCH_BASE
)+reg
);
179 static inline void sw_int_mask(u32 mask
)
183 t
= sw_read_reg(SWITCH_REG_INT_MASK
);
185 sw_write_reg(SWITCH_REG_INT_MASK
, t
);
188 static inline void sw_int_unmask(u32 mask
)
192 t
= sw_read_reg(SWITCH_REG_INT_MASK
);
194 sw_write_reg(SWITCH_REG_INT_MASK
, t
);
197 static inline void sw_int_ack(u32 mask
)
199 sw_write_reg(SWITCH_REG_INT_STATUS
, mask
);
202 static inline u32
sw_int_status(void)
206 t
= sw_read_reg(SWITCH_REG_INT_STATUS
);
207 t
&= ~sw_read_reg(SWITCH_REG_INT_MASK
);
211 /* ------------------------------------------------------------------------ */
213 static void sw_dump_desc(char *label
, struct dma_desc
*desc
, int tx
)
217 SW_DBG("%s %s desc/%p\n", label
, tx
? "tx" : "rx", desc
);
220 SW_DBG(" buf1 %08X addr=%08X; len=%08X %s%s\n", t
,
223 (t
& DESC_OWN
) ? "SWITCH" : "CPU",
224 (t
& DESC_EOR
) ? " RE" : "");
227 SW_DBG(" buf2 %08X addr=%08X%s\n", desc
->buf2
,
229 (t
& DESC_BUF2_EN
) ? " EN" : "" );
233 SW_DBG(" misc %08X%s pktlen=%04X ports=%02X vlan=%02X\n", t
,
234 (t
& DESC_CSUM
) ? " CSUM" : "",
235 (t
>> DESC_PKTLEN_SHIFT
) & DESC_PKTLEN_MASK
,
236 (t
>> DESC_DSTPORT_SHIFT
) & DESC_DSTPORT_MASK
,
239 SW_DBG(" misc %08X pktlen=%04X port=%d DA=%d%s%s type=%d\n",
241 (t
>> DESC_PKTLEN_SHIFT
) & DESC_PKTLEN_MASK
,
242 (t
>> DESC_SRCPORT_SHIFT
) & DESC_SRCPORT_MASK
,
243 (t
>> DESC_DA_SHIFT
) & DESC_DA_MASK
,
244 (t
& DESC_IPCSUM_FAIL
) ? " IPCF" : "",
245 (t
& DESC_VLAN_TAG
) ? " VLAN" : "",
246 (t
& DESC_TYPE_MASK
));
249 static void sw_dump_intr_mask(char *label
, u32 mask
)
251 SW_DBG("%s %08X%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
253 (mask
& SWITCH_INT_SHD
) ? " SHD" : "",
254 (mask
& SWITCH_INT_SLD
) ? " SLD" : "",
255 (mask
& SWITCH_INT_RHD
) ? " RHD" : "",
256 (mask
& SWITCH_INT_RLD
) ? " RLD" : "",
257 (mask
& SWITCH_INT_HDF
) ? " HDF" : "",
258 (mask
& SWITCH_INT_LDF
) ? " LDF" : "",
259 (mask
& SWITCH_INT_P0QF
) ? " P0QF" : "",
260 (mask
& SWITCH_INT_P1QF
) ? " P1QF" : "",
261 (mask
& SWITCH_INT_P2QF
) ? " P2QF" : "",
262 (mask
& SWITCH_INT_P3QF
) ? " P3QF" : "",
263 (mask
& SWITCH_INT_P4QF
) ? " P4QF" : "",
264 (mask
& SWITCH_INT_CPQF
) ? " CPQF" : "",
265 (mask
& SWITCH_INT_GQF
) ? " GQF" : "",
266 (mask
& SWITCH_INT_MD
) ? " MD" : "",
267 (mask
& SWITCH_INT_BCS
) ? " BCS" : "",
268 (mask
& SWITCH_INT_PSC
) ? " PSC" : "",
269 (mask
& SWITCH_INT_ID
) ? " ID" : "",
270 (mask
& SWITCH_INT_W0TE
) ? " W0TE" : "",
271 (mask
& SWITCH_INT_W1TE
) ? " W1TE" : "",
272 (mask
& SWITCH_INT_RDE
) ? " RDE" : "",
273 (mask
& SWITCH_INT_SDE
) ? " SDE" : "",
274 (mask
& SWITCH_INT_CPUH
) ? " CPUH" : "");
277 static void sw_dump_regs(void)
281 t
= SW_READ_REG(PHY_STATUS
);
282 SW_DBG("phy_status: %08X\n", t
);
284 t
= SW_READ_REG(CPUP_CONF
);
285 SW_DBG("cpup_conf: %08X%s%s%s\n", t
,
286 (t
& CPUP_CONF_DCPUP
) ? " DCPUP" : "",
287 (t
& CPUP_CONF_CRCP
) ? " CRCP" : "",
288 (t
& CPUP_CONF_BTM
) ? " BTM" : "");
290 t
= SW_READ_REG(PORT_CONF0
);
291 SW_DBG("port_conf0: %08X\n", t
);
292 t
= SW_READ_REG(PORT_CONF1
);
293 SW_DBG("port_conf1: %08X\n", t
);
294 t
= SW_READ_REG(PORT_CONF2
);
295 SW_DBG("port_conf2: %08X\n", t
);
297 t
= SW_READ_REG(VLAN_G1
);
298 SW_DBG("vlan g1: %08X\n", t
);
299 t
= SW_READ_REG(VLAN_G2
);
300 SW_DBG("vlan g2: %08X\n", t
);
302 t
= SW_READ_REG(BW_CNTL0
);
303 SW_DBG("bw_cntl0: %08X\n", t
);
304 t
= SW_READ_REG(BW_CNTL1
);
305 SW_DBG("bw_cntl1: %08X\n", t
);
307 t
= SW_READ_REG(PHY_CNTL0
);
308 SW_DBG("phy_cntl0: %08X\n", t
);
309 t
= SW_READ_REG(PHY_CNTL1
);
310 SW_DBG("phy_cntl1: %08X\n", t
);
311 t
= SW_READ_REG(PHY_CNTL2
);
312 SW_DBG("phy_cntl2: %08X\n", t
);
313 t
= SW_READ_REG(PHY_CNTL3
);
314 SW_DBG("phy_cntl3: %08X\n", t
);
315 t
= SW_READ_REG(PHY_CNTL4
);
316 SW_DBG("phy_cntl4: %08X\n", t
);
318 t
= SW_READ_REG(INT_STATUS
);
319 sw_dump_intr_mask("int_status: ", t
);
321 t
= SW_READ_REG(INT_MASK
);
322 sw_dump_intr_mask("int_mask: ", t
);
324 t
= SW_READ_REG(SHDA
);
325 SW_DBG("shda: %08X\n", t
);
326 t
= SW_READ_REG(SLDA
);
327 SW_DBG("slda: %08X\n", t
);
328 t
= SW_READ_REG(RHDA
);
329 SW_DBG("rhda: %08X\n", t
);
330 t
= SW_READ_REG(RLDA
);
331 SW_DBG("rlda: %08X\n", t
);
335 /* ------------------------------------------------------------------------ */
337 static inline void adm5120_rx_dma_update(struct dma_desc
*desc
,
338 struct sk_buff
*skb
, int end
)
342 desc
->buflen
= RX_MAX_PKTLEN
;
343 desc
->buf1
= DESC_ADDR(skb
->data
) |
344 DESC_OWN
| (end
? DESC_EOR
: 0);
347 static void adm5120_switch_rx_refill(void)
351 for (; cur_rxl
- dirty_rxl
> 0; dirty_rxl
++) {
352 struct dma_desc
*desc
;
355 entry
= dirty_rxl
% RX_RING_SIZE
;
356 desc
= &rxl_descs
[entry
];
358 skb
= rxl_skbuff
[entry
];
360 skb
= alloc_skb(SKB_ALLOC_LEN
, GFP_ATOMIC
);
362 skb_reserve(skb
, SKB_RESERVE_LEN
);
363 rxl_skbuff
[entry
] = skb
;
365 SW_ERR("no memory for skb\n");
369 desc
->buf1
= (desc
->buf1
& DESC_EOR
) | DESC_OWN
;
375 desc
->buflen
= RX_MAX_PKTLEN
;
377 desc
->buf1
= (desc
->buf1
& DESC_EOR
) | DESC_OWN
|
378 DESC_ADDR(skb
->data
);
382 static int adm5120_switch_rx(int limit
)
384 unsigned int done
= 0;
386 SW_DBG("rx start, limit=%d, cur_rxl=%u, dirty_rxl=%u\n",
387 limit
, cur_rxl
, dirty_rxl
);
389 sw_int_ack(SWITCH_INTS_POLL
);
391 while (done
< limit
) {
392 int entry
= cur_rxl
% RX_RING_SIZE
;
393 struct dma_desc
*desc
= &rxl_descs
[entry
];
394 struct net_device
*rdev
;
397 if (desc
->buf1
& DESC_OWN
)
400 if (dirty_rxl
+ RX_RING_SIZE
== cur_rxl
)
403 port
= desc_get_srcport(desc
);
404 rdev
= adm5120_port
[port
];
406 SW_DBG("rx descriptor %u, desc=%p, skb=%p\n", entry
, desc
,
409 if ((rdev
) && netif_running(rdev
)) {
410 struct sk_buff
*skb
= rxl_skbuff
[entry
];
413 pktlen
= desc_get_pktlen(desc
);
414 pktlen
-= ETH_CSUM_LEN
;
416 if ((pktlen
== 0) || desc_ipcsum_fail(desc
)) {
417 rdev
->stats
.rx_errors
++;
419 rdev
->stats
.rx_length_errors
++;
420 if (desc_ipcsum_fail(desc
))
421 rdev
->stats
.rx_crc_errors
++;
422 SW_DBG("rx error, recycling skb %u\n", entry
);
424 skb_put(skb
, pktlen
);
427 skb
->protocol
= eth_type_trans(skb
, rdev
);
428 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
430 dma_cache_wback_inv((unsigned long)skb
->data
,
433 netif_receive_skb(skb
);
435 rdev
->last_rx
= jiffies
;
436 rdev
->stats
.rx_packets
++;
437 rdev
->stats
.rx_bytes
+= pktlen
;
439 rxl_skbuff
[entry
] = NULL
;
443 SW_DBG("no rx device, recycling skb %u\n", entry
);
447 if (cur_rxl
- dirty_rxl
> RX_RING_SIZE
/ 4)
448 adm5120_switch_rx_refill();
451 adm5120_switch_rx_refill();
453 SW_DBG("rx finished, cur_rxl=%u, dirty_rxl=%u, processed %d\n",
454 cur_rxl
, dirty_rxl
, done
);
460 static void adm5120_switch_tx(void)
464 /* find and cleanup dirty tx descriptors */
465 entry
= dirty_txl
% TX_RING_SIZE
;
466 while (dirty_txl
!= cur_txl
) {
467 struct dma_desc
*desc
= &txl_descs
[entry
];
468 struct sk_buff
*skb
= txl_skbuff
[entry
];
470 if (desc
->buf1
& DESC_OWN
)
473 if (netif_running(skb
->dev
)) {
474 skb
->dev
->stats
.tx_bytes
+= skb
->len
;
475 skb
->dev
->stats
.tx_packets
++;
478 dev_kfree_skb_irq(skb
);
479 txl_skbuff
[entry
] = NULL
;
480 entry
= (++dirty_txl
) % TX_RING_SIZE
;
483 if ((cur_txl
- dirty_txl
) < TX_QUEUE_LEN
- 4) {
484 /* wake up queue of all devices */
486 for (i
= 0; i
< SWITCH_NUM_PORTS
; i
++) {
487 if (!adm5120_devs
[i
])
489 netif_wake_queue(adm5120_devs
[i
]);
494 static int adm5120_if_poll(struct net_device
*dev
, int *budget
)
496 int limit
= min(dev
->quota
, *budget
);
500 done
= adm5120_switch_rx(limit
);
505 status
= sw_int_status() & SWITCH_INTS_POLL
;
506 if ((done
< limit
) && (!status
)) {
507 SW_DBG("disable polling mode for %s\n", poll_dev
->name
);
508 netif_rx_complete(dev
);
509 sw_int_unmask(SWITCH_INTS_POLL
);
516 static irqreturn_t
adm5120_poll_irq(int irq
, void *dev_id
)
518 struct net_device
*dev
= dev_id
;
521 status
= sw_int_status();
522 status
&= SWITCH_INTS_POLL
;
526 sw_dump_intr_mask("poll ints", status
);
528 SW_DBG("enable polling mode for %s\n", dev
->name
);
529 sw_int_mask(SWITCH_INTS_POLL
);
530 netif_rx_schedule(dev
);
535 static irqreturn_t
adm5120_switch_irq(int irq
, void *dev_id
)
539 status
= sw_int_status();
540 status
&= SWITCH_INTS_ALL
& ~SWITCH_INTS_POLL
;
546 if (status
& SWITCH_INT_SLD
) {
549 spin_unlock(&sw_lock
);
555 static void adm5120_set_vlan(char *matrix
)
560 val
= matrix
[0] + (matrix
[1]<<8) + (matrix
[2]<<16) + (matrix
[3]<<24);
561 sw_write_reg(SWITCH_REG_VLAN_G1
, val
);
562 val
= matrix
[4] + (matrix
[5]<<8);
563 sw_write_reg(SWITCH_REG_VLAN_G2
, val
);
565 /* Now set/update the port vs. device lookup table */
566 for (port
=0; port
<SWITCH_NUM_PORTS
; port
++) {
567 for (vlan_port
=0; vlan_port
<SWITCH_NUM_PORTS
&& !(matrix
[vlan_port
] & (0x00000001 << port
)); vlan_port
++);
568 if (vlan_port
<SWITCH_NUM_PORTS
)
569 adm5120_port
[port
] = adm5120_devs
[vlan_port
];
571 adm5120_port
[port
] = NULL
;
575 static void adm5120_set_bw(char *matrix
)
579 /* Port 0 to 3 are set using the bandwidth control 0 register */
580 val
= matrix
[0] + (matrix
[1]<<8) + (matrix
[2]<<16) + (matrix
[3]<<24);
581 sw_write_reg(SWITCH_REG_BW_CNTL0
, val
);
583 /* Port 4 and 5 are set using the bandwidth control 1 register */
586 sw_write_reg(SWITCH_REG_BW_CNTL1
, val
| 0x80000000);
588 sw_write_reg(SWITCH_REG_BW_CNTL1
, val
& ~0x8000000);
590 SW_DBG("D: ctl0 0x%ux, ctl1 0x%ux\n", sw_read_reg(SWITCH_REG_BW_CNTL0
),
591 sw_read_reg(SWITCH_REG_BW_CNTL1
));
594 static void adm5120_switch_tx_ring_reset(struct dma_desc
*desc
,
595 struct sk_buff
**skbl
, int num
)
597 memset(desc
, 0, num
* sizeof(*desc
));
598 desc
[num
-1].buf1
|= DESC_EOR
;
599 memset(skbl
, 0, sizeof(struct skb
*)*num
);
605 static void adm5120_switch_rx_ring_reset(struct dma_desc
*desc
,
606 struct sk_buff
**skbl
, int num
)
610 memset(desc
, 0, num
* sizeof(*desc
));
611 for (i
= 0; i
< num
; i
++) {
612 skbl
[i
] = dev_alloc_skb(SKB_ALLOC_LEN
);
617 skb_reserve(skbl
[i
], SKB_RESERVE_LEN
);
618 adm5120_rx_dma_update(&desc
[i
], skbl
[i
], (num
-1==i
));
625 static int adm5120_switch_tx_ring_alloc(void)
629 txl_descs
= dma_alloc_coherent(NULL
, TX_DESCS_SIZE
, &txl_descs_dma
,
636 txl_skbuff
= kzalloc(TX_SKBS_SIZE
, GFP_KERNEL
);
648 static void adm5120_switch_tx_ring_free(void)
653 for (i
= 0; i
< TX_RING_SIZE
; i
++)
655 kfree_skb(txl_skbuff
[i
]);
660 dma_free_coherent(NULL
, TX_DESCS_SIZE
, txl_descs
,
664 static int adm5120_switch_rx_ring_alloc(void)
670 rxl_descs
= dma_alloc_coherent(NULL
, RX_DESCS_SIZE
, &rxl_descs_dma
,
677 rxl_skbuff
= kzalloc(RX_SKBS_SIZE
, GFP_KERNEL
);
683 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
685 skb
= alloc_skb(SKB_ALLOC_LEN
, GFP_ATOMIC
);
691 skb_reserve(skb
, SKB_RESERVE_LEN
);
700 static void adm5120_switch_rx_ring_free(void)
705 for (i
= 0; i
< RX_RING_SIZE
; i
++)
707 kfree_skb(rxl_skbuff
[i
]);
712 dma_free_coherent(NULL
, RX_DESCS_SIZE
, rxl_descs
,
716 /* ------------------------------------------------------------------------ */
718 static int adm5120_if_open(struct net_device
*dev
)
724 err
= request_irq(dev
->irq
, adm5120_poll_irq
,
725 (IRQF_SHARED
| IRQF_DISABLED
), dev
->name
, dev
);
727 SW_ERR("unable to get irq for %s\n", dev
->name
);
732 /* enable interrupts on first open */
733 sw_int_unmask(SWITCH_INTS_USED
);
735 /* enable (additional) port */
736 t
= sw_read_reg(SWITCH_REG_PORT_CONF0
);
737 for (i
= 0; i
< SWITCH_NUM_PORTS
; i
++) {
738 if (dev
== adm5120_devs
[i
])
739 t
&= ~adm5120_eth_vlans
[i
];
741 sw_write_reg(SWITCH_REG_PORT_CONF0
, t
);
743 netif_start_queue(dev
);
751 static int adm5120_if_stop(struct net_device
*dev
)
756 netif_stop_queue(dev
);
758 /* disable port if not assigned to other devices */
759 t
= sw_read_reg(SWITCH_REG_PORT_CONF0
);
760 t
|= SWITCH_PORTS_NOCPU
;
761 for (i
= 0; i
< SWITCH_NUM_PORTS
; i
++) {
762 if ((dev
!= adm5120_devs
[i
]) && netif_running(adm5120_devs
[i
]))
763 t
&= ~adm5120_eth_vlans
[i
];
765 sw_write_reg(SWITCH_REG_PORT_CONF0
, t
);
768 sw_int_mask(SWITCH_INTS_USED
);
770 free_irq(dev
->irq
, dev
);
775 static int adm5120_if_hard_start_xmit(struct sk_buff
*skb
,
776 struct net_device
*dev
)
778 struct dma_desc
*desc
;
779 struct adm5120_sw
*priv
= netdev_priv(dev
);
783 /* lock switch irq */
784 spin_lock_irq(&sw_lock
);
786 /* calculate the next TX descriptor entry. */
787 entry
= cur_txl
% TX_RING_SIZE
;
789 desc
= &txl_descs
[entry
];
790 if (desc
->buf1
& DESC_OWN
) {
791 /* We want to write a packet but the TX queue is still
792 * occupied by the DMA. We are faster than the DMA... */
794 dev
->stats
.tx_dropped
++;
798 txl_skbuff
[entry
] = skb
;
799 data
= (desc
->buf1
& DESC_EOR
);
800 data
|= DESC_ADDR(skb
->data
);
803 ((skb
->len
<ETH_ZLEN
?ETH_ZLEN
:skb
->len
) << DESC_PKTLEN_SHIFT
) |
806 desc
->buflen
= skb
->len
< ETH_ZLEN
? ETH_ZLEN
: skb
->len
;
808 desc
->buf1
= data
| DESC_OWN
;
809 sw_write_reg(SWITCH_REG_SEND_TRIG
, SEND_TRIG_STL
);
812 if (cur_txl
== dirty_txl
+ TX_QUEUE_LEN
) {
813 /* FIXME: stop queue for all devices */
814 netif_stop_queue(dev
);
817 dev
->trans_start
= jiffies
;
819 spin_unlock_irq(&sw_lock
);
824 static void adm5120_if_tx_timeout(struct net_device
*dev
)
826 SW_INFO("TX timeout on %s\n",dev
->name
);
829 static void adm5120_set_multicast_list(struct net_device
*dev
)
831 struct adm5120_sw
*priv
= netdev_priv(dev
);
835 ports
= adm5120_eth_vlans
[priv
->port
] & SWITCH_PORTS_NOCPU
;
837 t
= sw_read_reg(SWITCH_REG_CPUP_CONF
);
838 if (dev
->flags
& IFF_PROMISC
)
839 /* enable unknown packets */
840 t
&= ~(ports
<< CPUP_CONF_DUNP_SHIFT
);
842 /* disable unknown packets */
843 t
|= (ports
<< CPUP_CONF_DUNP_SHIFT
);
845 if (dev
->flags
& IFF_PROMISC
|| dev
->flags
& IFF_ALLMULTI
||
847 /* enable multicast packets */
848 t
&= ~(ports
<< CPUP_CONF_DMCP_SHIFT
);
850 /* disable multicast packets */
851 t
|= (ports
<< CPUP_CONF_DMCP_SHIFT
);
853 /* If there is any port configured to be in promiscuous mode, then the */
854 /* Bridge Test Mode has to be activated. This will result in */
855 /* transporting also packets learned in another VLAN to be forwarded */
857 /* The difficult scenario is when we want to build a bridge on the CPU.*/
858 /* Assume we have port0 and the CPU port in VLAN0 and port1 and the */
859 /* CPU port in VLAN1. Now we build a bridge on the CPU between */
860 /* VLAN0 and VLAN1. Both ports of the VLANs are set in promisc mode. */
861 /* Now assume a packet with ethernet source address 99 enters port 0 */
862 /* It will be forwarded to the CPU because it is unknown. Then the */
863 /* bridge in the CPU will send it to VLAN1 and it goes out at port 1. */
864 /* When now a packet with ethernet destination address 99 comes in at */
865 /* port 1 in VLAN1, then the switch has learned that this address is */
866 /* located at port 0 in VLAN0. Therefore the switch will drop */
867 /* this packet. In order to avoid this and to send the packet still */
868 /* to the CPU, the Bridge Test Mode has to be activated. */
870 /* Check if there is any vlan in promisc mode. */
871 if (t
& (SWITCH_PORTS_NOCPU
<< CPUP_CONF_DUNP_SHIFT
))
872 t
&= ~CPUP_CONF_BTM
; /* Disable Bridge Testing Mode */
874 t
|= CPUP_CONF_BTM
; /* Enable Bridge Testing Mode */
876 sw_write_reg(SWITCH_REG_CPUP_CONF
, t
);
880 static void adm5120_write_mac(struct net_device
*dev
)
882 struct adm5120_sw
*priv
= netdev_priv(dev
);
883 unsigned char *mac
= dev
->dev_addr
;
886 t
= mac
[2] | (mac
[3] << MAC_WT1_MAC3_SHIFT
) |
887 (mac
[4] << MAC_WT1_MAC4_SHIFT
) | (mac
[5] << MAC_WT1_MAC4_SHIFT
);
888 sw_write_reg(SWITCH_REG_MAC_WT1
, t
);
890 t
= (mac
[0] << MAC_WT0_MAC0_SHIFT
) | (mac
[1] << MAC_WT0_MAC1_SHIFT
) |
891 MAC_WT0_MAWC
| MAC_WT0_WVE
| (priv
->port
<<3);
893 sw_write_reg(SWITCH_REG_MAC_WT0
, t
);
895 while (!(sw_read_reg(SWITCH_REG_MAC_WT0
) & MAC_WT0_MWD
));
898 static int adm5120_if_set_mac_address(struct net_device
*dev
, void *p
)
900 struct sockaddr
*addr
= p
;
902 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
903 adm5120_write_mac(dev
);
907 static int adm5120_if_do_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
910 struct adm5120_sw_info info
;
911 struct adm5120_sw
*priv
= netdev_priv(dev
);
916 info
.ports
= adm5120_nrdevs
;
917 info
.vlan
= priv
->port
;
918 err
= copy_to_user(rq
->ifr_data
, &info
, sizeof(info
));
923 if (!capable(CAP_NET_ADMIN
))
925 err
= copy_from_user(adm5120_eth_vlans
, rq
->ifr_data
,
926 sizeof(adm5120_eth_vlans
));
929 adm5120_set_vlan(adm5120_eth_vlans
);
932 err
= copy_to_user(rq
->ifr_data
, adm5120_eth_vlans
,
933 sizeof(adm5120_eth_vlans
));
938 err
= copy_to_user(rq
->ifr_data
, bw_matrix
, sizeof(bw_matrix
));
943 if (!capable(CAP_NET_ADMIN
))
945 err
= copy_from_user(bw_matrix
, rq
->ifr_data
, sizeof(bw_matrix
));
948 adm5120_set_bw(bw_matrix
);
956 static struct net_device
*adm5120_if_alloc(void)
958 struct net_device
*dev
;
959 struct adm5120_sw
*priv
;
961 dev
= alloc_etherdev(sizeof(*priv
));
965 dev
->irq
= ADM5120_IRQ_SWITCH
;
966 dev
->open
= adm5120_if_open
;
967 dev
->hard_start_xmit
= adm5120_if_hard_start_xmit
;
968 dev
->stop
= adm5120_if_stop
;
969 dev
->set_multicast_list
= adm5120_set_multicast_list
;
970 dev
->do_ioctl
= adm5120_if_do_ioctl
;
971 dev
->tx_timeout
= adm5120_if_tx_timeout
;
972 dev
->watchdog_timeo
= TX_TIMEOUT
;
973 dev
->set_mac_address
= adm5120_if_set_mac_address
;
974 dev
->poll
= adm5120_if_poll
;
977 SET_MODULE_OWNER(dev
);
982 static void adm5120_switch_cleanup(void)
986 /* disable interrupts */
987 sw_int_mask(SWITCH_INTS_ALL
);
989 for (i
= 0; i
< SWITCH_NUM_PORTS
; i
++) {
990 struct net_device
*dev
= adm5120_devs
[i
];
992 unregister_netdev(dev
);
997 adm5120_switch_tx_ring_free();
998 adm5120_switch_rx_ring_free();
1000 free_irq(ADM5120_IRQ_SWITCH
, &sw_dev
);
1003 static int __init
adm5120_switch_init(void)
1008 err
= request_irq(ADM5120_IRQ_SWITCH
, adm5120_switch_irq
,
1009 (IRQF_SHARED
| IRQF_DISABLED
), "switch", &sw_dev
);
1011 SW_ERR("request_irq failed with error %d\n", err
);
1015 adm5120_nrdevs
= adm5120_eth_num_ports
;
1017 t
= CPUP_CONF_DCPUP
| CPUP_CONF_CRCP
|
1018 SWITCH_PORTS_NOCPU
<< CPUP_CONF_DUNP_SHIFT
|
1019 SWITCH_PORTS_NOCPU
<< CPUP_CONF_DMCP_SHIFT
;
1020 sw_write_reg(SWITCH_REG_CPUP_CONF
, t
);
1022 t
= (SWITCH_PORTS_NOCPU
<< PORT_CONF0_EMCP_SHIFT
) |
1023 (SWITCH_PORTS_NOCPU
<< PORT_CONF0_BP_SHIFT
) |
1024 (SWITCH_PORTS_NOCPU
);
1025 sw_write_reg(SWITCH_REG_PORT_CONF0
, t
);
1027 /* setup ports to Autoneg/100M/Full duplex/Auto MDIX */
1028 t
= SWITCH_PORTS_PHY
|
1029 (SWITCH_PORTS_PHY
<< PHY_CNTL2_SC_SHIFT
) |
1030 (SWITCH_PORTS_PHY
<< PHY_CNTL2_DC_SHIFT
) |
1031 (SWITCH_PORTS_PHY
<< PHY_CNTL2_PHYR_SHIFT
) |
1032 (SWITCH_PORTS_PHY
<< PHY_CNTL2_AMDIX_SHIFT
) |
1034 SW_WRITE_REG(PHY_CNTL2
, t
);
1036 t
= sw_read_reg(SWITCH_REG_PHY_CNTL3
);
1038 sw_write_reg(SWITCH_REG_PHY_CNTL3
, t
);
1040 /* Force all the packets from all ports are low priority */
1041 sw_write_reg(SWITCH_REG_PRI_CNTL
, 0);
1043 sw_int_mask(SWITCH_INTS_ALL
);
1044 sw_int_ack(SWITCH_INTS_ALL
);
1046 err
= adm5120_switch_rx_ring_alloc();
1050 err
= adm5120_switch_tx_ring_alloc();
1054 adm5120_switch_tx_ring_reset(txl_descs
, txl_skbuff
, TX_RING_SIZE
);
1055 adm5120_switch_rx_ring_reset(rxl_descs
, rxl_skbuff
, RX_RING_SIZE
);
1057 sw_write_reg(SWITCH_REG_SHDA
, 0);
1058 sw_write_reg(SWITCH_REG_SLDA
, KSEG1ADDR(txl_descs
));
1059 sw_write_reg(SWITCH_REG_RHDA
, 0);
1060 sw_write_reg(SWITCH_REG_RLDA
, KSEG1ADDR(rxl_descs
));
1062 for (i
= 0; i
< SWITCH_NUM_PORTS
; i
++) {
1063 struct net_device
*dev
;
1064 struct adm5120_sw
*priv
;
1066 dev
= adm5120_if_alloc();
1072 adm5120_devs
[i
] = dev
;
1073 priv
= netdev_priv(dev
);
1077 memcpy(dev
->dev_addr
, adm5120_eth_macs
[i
], 6);
1078 adm5120_write_mac(dev
);
1080 err
= register_netdev(dev
);
1082 SW_INFO("%s register failed, error=%d\n",
1088 /* setup vlan/port mapping after devs are filled up */
1089 adm5120_set_vlan(adm5120_eth_vlans
);
1091 /* enable CPU port */
1092 t
= sw_read_reg(SWITCH_REG_CPUP_CONF
);
1093 t
&= ~CPUP_CONF_DCPUP
;
1094 sw_write_reg(SWITCH_REG_CPUP_CONF
, t
);
1099 adm5120_switch_cleanup();
1101 SW_ERR("init failed\n");
1105 static void __exit
adm5120_switch_exit(void)
1107 adm5120_switch_cleanup();
1110 module_init(adm5120_switch_init
);
1111 module_exit(adm5120_switch_exit
);