2 * ADM5120 HCD (Host Controller Driver) for USB
4 * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
6 * This file was derived from: drivers/usb/host/ohci-q.c
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
16 #include <linux/irq.h>
17 #include <linux/slab.h>
19 /*-------------------------------------------------------------------------*/
22 * URB goes back to driver, and isn't reissued.
23 * It's completely gone from HC data structures.
24 * PRECONDITION: ahcd lock held, irqs blocked.
27 finish_urb(struct admhcd
*ahcd
, struct urb
*urb
, int status
)
28 __releases(ahcd
->lock
)
29 __acquires(ahcd
->lock
)
31 urb_priv_free(ahcd
, urb
->hcpriv
);
33 if (likely(status
== -EINPROGRESS
))
36 switch (usb_pipetype(urb
->pipe
)) {
37 case PIPE_ISOCHRONOUS
:
38 admhcd_to_hcd(ahcd
)->self
.bandwidth_isoc_reqs
--;
41 admhcd_to_hcd(ahcd
)->self
.bandwidth_int_reqs
--;
45 #ifdef ADMHC_VERBOSE_DEBUG
46 urb_print(ahcd
, urb
, "RET", usb_pipeout(urb
->pipe
), status
);
49 /* urb->complete() can reenter this HCD */
50 usb_hcd_unlink_urb_from_ep(admhcd_to_hcd(ahcd
), urb
);
51 spin_unlock(&ahcd
->lock
);
52 usb_hcd_giveback_urb(admhcd_to_hcd(ahcd
), urb
, status
);
53 spin_lock(&ahcd
->lock
);
57 /*-------------------------------------------------------------------------*
58 * ED handling functions
59 *-------------------------------------------------------------------------*/
62 /* search for the right schedule branch to use for a periodic ed.
63 * does some load balancing; returns the branch, or negative errno.
65 static int balance(struct admhcd
*ahcd
, int interval
, int load
)
67 int i
, branch
= -ENOSPC
;
69 /* iso periods can be huge; iso tds specify frame numbers */
70 if (interval
> NUM_INTS
)
73 /* search for the least loaded schedule branch of that period
74 * that has enough bandwidth left unreserved.
76 for (i
= 0; i
< interval
; i
++) {
77 if (branch
< 0 || ahcd
->load
[branch
] > ahcd
->load
[i
]) {
80 /* usb 1.1 says 90% of one frame */
81 for (j
= i
; j
< NUM_INTS
; j
+= interval
) {
82 if ((ahcd
->load
[j
] + load
) > 900)
94 /*-------------------------------------------------------------------------*/
97 /* both iso and interrupt requests have periods; this routine puts them
98 * into the schedule tree in the apppropriate place. most iso devices use
99 * 1msec periods, but that's not required.
101 static void periodic_link(struct admhcd
*ahcd
, struct ed
*ed
)
105 admhc_vdbg(ahcd
, "link %sed %p branch %d [%dus.], interval %d\n",
106 (ed
->hwINFO
& cpu_to_hc32(ahcd
, ED_ISO
)) ? "iso " : "",
107 ed
, ed
->branch
, ed
->load
, ed
->interval
);
109 for (i
= ed
->branch
; i
< NUM_INTS
; i
+= ed
->interval
) {
110 struct ed
**prev
= &ahcd
->periodic
[i
];
111 __hc32
*prev_p
= &ahcd
->hcca
->int_table
[i
];
112 struct ed
*here
= *prev
;
114 /* sorting each branch by period (slow before fast)
115 * lets us share the faster parts of the tree.
116 * (plus maybe: put interrupt eds before iso)
118 while (here
&& ed
!= here
) {
119 if (ed
->interval
> here
->interval
)
121 prev
= &here
->ed_next
;
122 prev_p
= &here
->hwNextED
;
128 ed
->hwNextED
= *prev_p
;
131 *prev_p
= cpu_to_hc32(ahcd
, ed
->dma
);
134 ahcd
->load
[i
] += ed
->load
;
136 admhcd_to_hcd(ahcd
)->self
.bandwidth_allocated
+= ed
->load
/ ed
->interval
;
140 /* link an ed into the HC chain */
142 static int ed_schedule(struct admhcd
*ahcd
, struct ed
*ed
)
146 if (admhcd_to_hcd(ahcd
)->state
== HC_STATE_QUIESCING
)
151 old_tail
= ahcd
->ed_tails
[ed
->type
];
153 ed
->ed_next
= old_tail
->ed_next
;
155 ed
->ed_next
->ed_prev
= ed
;
156 ed
->hwNextED
= cpu_to_hc32(ahcd
, ed
->ed_next
->dma
);
158 ed
->ed_prev
= old_tail
;
160 old_tail
->ed_next
= ed
;
161 old_tail
->hwNextED
= cpu_to_hc32(ahcd
, ed
->dma
);
163 ahcd
->ed_tails
[ed
->type
] = ed
;
165 admhc_dma_enable(ahcd
);
170 /*-------------------------------------------------------------------------*/
173 /* scan the periodic table to find and unlink this ED */
174 static void periodic_unlink(struct admhcd
*ahcd
, struct ed
*ed
)
178 for (i
= ed
->branch
; i
< NUM_INTS
; i
+= ed
->interval
) {
180 struct ed
**prev
= &ahcd
->periodic
[i
];
181 __hc32
*prev_p
= &ahcd
->hcca
->int_table
[i
];
183 while (*prev
&& (temp
= *prev
) != ed
) {
184 prev_p
= &temp
->hwNextED
;
185 prev
= &temp
->ed_next
;
188 *prev_p
= ed
->hwNextED
;
191 ahcd
->load
[i
] -= ed
->load
;
194 admhcd_to_hcd(ahcd
)->self
.bandwidth_allocated
-= ed
->load
/ ed
->interval
;
195 admhc_vdbg(ahcd
, "unlink %sed %p branch %d [%dus.], interval %d\n",
196 (ed
->hwINFO
& cpu_to_hc32(ahcd
, ED_ISO
)) ? "iso " : "",
197 ed
, ed
->branch
, ed
->load
, ed
->interval
);
201 /* unlink an ed from the HC chain.
202 * just the link to the ed is unlinked.
203 * the link from the ed still points to another operational ed or 0
204 * so the HC can eventually finish the processing of the unlinked ed
205 * (assuming it already started that, which needn't be true).
207 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
208 * it won't. ED_SKIP means the HC will finish its current transaction,
209 * but won't start anything new. The TD queue may still grow; device
210 * drivers don't know about this HCD-internal state.
212 * When the HC can't see the ED, something changes ED_UNLINK to one of:
214 * - ED_OPER: when there's any request queued, the ED gets rescheduled
215 * immediately. HC should be working on them.
217 * - ED_IDLE: when there's no TD queue. there's no reason for the HC
218 * to care about this ED; safe to disable the endpoint.
220 * When finish_unlinks() runs later, after SOF interrupt, it will often
221 * complete one or more URB unlinks before making that state change.
223 static void ed_deschedule(struct admhcd
*ahcd
, struct ed
*ed
)
226 #ifdef ADMHC_VERBOSE_DEBUG
227 admhc_dump_ed(ahcd
, "ED-DESCHED", ed
, 1);
230 ed
->hwINFO
|= cpu_to_hc32(ahcd
, ED_SKIP
);
232 ed
->state
= ED_UNLINK
;
234 /* remove this ED from the HC list */
235 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
237 /* and remove it from our list also */
238 ed
->ed_prev
->ed_next
= ed
->ed_next
;
241 ed
->ed_next
->ed_prev
= ed
->ed_prev
;
243 if (ahcd
->ed_tails
[ed
->type
] == ed
)
244 ahcd
->ed_tails
[ed
->type
] = ed
->ed_prev
;
247 /*-------------------------------------------------------------------------*/
249 static struct ed
*ed_create(struct admhcd
*ahcd
, unsigned int type
, u32 info
)
254 ed
= ed_alloc(ahcd
, GFP_ATOMIC
);
258 /* dummy td; end of td list for this ed */
259 td
= td_alloc(ahcd
, GFP_ATOMIC
);
267 case PIPE_ISOCHRONOUS
:
276 ed
->hwINFO
= cpu_to_hc32(ahcd
, info
);
277 ed
->hwTailP
= cpu_to_hc32(ahcd
, td
->td_dma
);
278 ed
->hwHeadP
= ed
->hwTailP
; /* ED_C, ED_H zeroed */
288 /* get and maybe (re)init an endpoint. init _should_ be done only as part
289 * of enumeration, usb_set_configuration() or usb_set_interface().
291 static struct ed
*ed_get(struct admhcd
*ahcd
, struct usb_host_endpoint
*ep
,
292 struct usb_device
*udev
, unsigned int pipe
, int interval
)
297 spin_lock_irqsave(&ahcd
->lock
, flags
);
303 /* FIXME: usbcore changes dev->devnum before SET_ADDRESS
304 * succeeds ... otherwise we wouldn't need "pipe".
306 info
= usb_pipedevice(pipe
);
307 info
|= (ep
->desc
.bEndpointAddress
& ~USB_DIR_IN
) << ED_EN_SHIFT
;
308 info
|= le16_to_cpu(ep
->desc
.wMaxPacketSize
) << ED_MPS_SHIFT
;
309 if (udev
->speed
== USB_SPEED_FULL
)
310 info
|= ED_SPEED_FULL
;
312 ed
= ed_create(ahcd
, usb_pipetype(pipe
), info
);
317 spin_unlock_irqrestore(&ahcd
->lock
, flags
);
322 /*-------------------------------------------------------------------------*/
324 /* request unlinking of an endpoint from an operational HC.
325 * put the ep on the rm_list
326 * real work is done at the next start frame (SOFI) hardware interrupt
327 * caller guarantees HCD is running, so hardware access is safe,
328 * and that ed->state is ED_OPER
330 static void start_ed_unlink(struct admhcd
*ahcd
, struct ed
*ed
)
333 #ifdef ADMHC_VERBOSE_DEBUG
334 admhc_dump_ed(ahcd
, "ED-UNLINK", ed
, 1);
337 ed
->hwINFO
|= cpu_to_hc32(ahcd
, ED_DEQUEUE
);
338 ed_deschedule(ahcd
, ed
);
340 /* add this ED into the remove list */
341 ed
->ed_rm_next
= ahcd
->ed_rm_list
;
342 ahcd
->ed_rm_list
= ed
;
344 /* enable SOF interrupt */
345 admhc_intr_ack(ahcd
, ADMHC_INTR_SOFI
);
346 admhc_intr_enable(ahcd
, ADMHC_INTR_SOFI
);
347 /* flush those writes */
348 admhc_writel_flush(ahcd
);
350 /* SOF interrupt might get delayed; record the frame counter value that
351 * indicates when the HC isn't looking at it, so concurrent unlinks
352 * behave. frame_no wraps every 2^16 msec, and changes right before
355 ed
->tick
= admhc_frame_no(ahcd
) + 1;
358 /*-------------------------------------------------------------------------*
359 * TD handling functions
360 *-------------------------------------------------------------------------*/
362 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
365 td_fill(struct admhcd
*ahcd
, u32 info
, dma_addr_t data
, int len
,
366 struct urb
*urb
, int index
)
368 struct td
*td
, *td_pt
;
369 struct urb_priv
*urb_priv
= urb
->hcpriv
;
374 if (index
== (urb_priv
->td_cnt
- 1) &&
375 ((urb
->transfer_flags
& URB_NO_INTERRUPT
) == 0))
378 if (index
== (urb_priv
->td_cnt
- 1))
382 /* use this td as the next dummy */
383 td_pt
= urb_priv
->td
[index
];
385 /* fill the old dummy TD */
386 td
= urb_priv
->td
[index
] = urb_priv
->ed
->dummy
;
387 urb_priv
->ed
->dummy
= td_pt
;
389 td
->ed
= urb_priv
->ed
;
390 td
->next_dl_td
= NULL
;
398 cbl
|= (len
& TD_BL_MASK
);
402 /* setup hardware specific fields */
403 td
->hwINFO
= cpu_to_hc32(ahcd
, info
);
404 td
->hwDBP
= cpu_to_hc32(ahcd
, data
);
405 td
->hwCBL
= cpu_to_hc32(ahcd
, cbl
);
406 td
->hwNextTD
= cpu_to_hc32(ahcd
, td_pt
->td_dma
);
408 /* append to queue */
409 list_add_tail(&td
->td_list
, &td
->ed
->td_list
);
411 /* hash it for later reverse mapping */
412 hash
= TD_HASH_FUNC(td
->td_dma
);
413 td
->td_hash
= ahcd
->td_hash
[hash
];
414 ahcd
->td_hash
[hash
] = td
;
416 /* HC might read the TD (or cachelines) right away ... */
418 td
->ed
->hwTailP
= td
->hwNextTD
;
421 /*-------------------------------------------------------------------------*/
423 /* Prepare all TDs of a transfer, and queue them onto the ED.
424 * Caller guarantees HC is active.
425 * Usually the ED is already on the schedule, so TDs might be
426 * processed as soon as they're queued.
428 static void td_submit_urb(struct admhcd
*ahcd
, struct urb
*urb
)
430 struct urb_priv
*urb_priv
= urb
->hcpriv
;
432 int data_len
= urb
->transfer_buffer_length
;
435 int is_out
= usb_pipeout(urb
->pipe
);
438 /* OHCI handles the bulk/interrupt data toggles itself. We just
439 * use the device toggle bits for resetting, and rely on the fact
440 * that resetting toggle is meaningless if the endpoint is active.
443 if (usb_gettoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
), is_out
)) {
447 usb_settoggle(urb
->dev
, usb_pipeendpoint (urb
->pipe
),
451 urb_priv
->td_idx
= 0;
452 list_add(&urb_priv
->pending
, &ahcd
->pending
);
455 data
= urb
->transfer_dma
;
459 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
460 * using TD_CC_GET, as well as by seeing them on the done list.
461 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
463 switch (urb_priv
->ed
->type
) {
466 ? TD_T_CARRY
| TD_SCC_NOTACCESSED
| TD_DP_OUT
467 : TD_T_CARRY
| TD_SCC_NOTACCESSED
| TD_DP_IN
;
469 /* setup service interval and starting frame number */
470 info
|= (urb
->start_frame
& TD_FN_MASK
);
471 info
|= (urb
->interval
& TD_ISI_MASK
) << TD_ISI_SHIFT
;
473 td_fill(ahcd
, info
, data
, data_len
, urb
, cnt
);
476 admhcd_to_hcd(ahcd
)->self
.bandwidth_int_reqs
++;
481 ? TD_SCC_NOTACCESSED
| TD_DP_OUT
482 : TD_SCC_NOTACCESSED
| TD_DP_IN
;
484 /* TDs _could_ transfer up to 8K each */
485 while (data_len
> TD_DATALEN_MAX
) {
486 td_fill(ahcd
, info
| ((cnt
) ? TD_T_CARRY
: toggle
),
487 data
, TD_DATALEN_MAX
, urb
, cnt
);
488 data
+= TD_DATALEN_MAX
;
489 data_len
-= TD_DATALEN_MAX
;
493 td_fill(ahcd
, info
| ((cnt
) ? TD_T_CARRY
: toggle
), data
,
497 if ((urb
->transfer_flags
& URB_ZERO_PACKET
)
498 && (cnt
< urb_priv
->td_cnt
)) {
499 td_fill(ahcd
, info
| ((cnt
) ? TD_T_CARRY
: toggle
),
505 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
506 * any DATA phase works normally, and the STATUS ack is special.
509 /* fill a TD for the setup */
510 info
= TD_SCC_NOTACCESSED
| TD_DP_SETUP
| TD_T_DATA0
;
511 td_fill(ahcd
, info
, urb
->setup_dma
, 8, urb
, cnt
++);
514 /* fill a TD for the data */
515 info
= TD_SCC_NOTACCESSED
| TD_T_DATA1
;
516 info
|= is_out
? TD_DP_OUT
: TD_DP_IN
;
517 /* NOTE: mishandles transfers >8K, some >4K */
518 td_fill(ahcd
, info
, data
, data_len
, urb
, cnt
++);
521 /* fill a TD for the ACK */
522 info
= (is_out
|| data_len
== 0)
523 ? TD_SCC_NOTACCESSED
| TD_DP_IN
| TD_T_DATA1
524 : TD_SCC_NOTACCESSED
| TD_DP_OUT
| TD_T_DATA1
;
525 td_fill(ahcd
, info
, data
, 0, urb
, cnt
++);
529 /* ISO has no retransmit, so no toggle;
530 * Each TD could handle multiple consecutive frames (interval 1);
531 * we could often reduce the number of TDs here.
533 case PIPE_ISOCHRONOUS
:
535 ? TD_T_CARRY
| TD_SCC_NOTACCESSED
| TD_DP_OUT
536 : TD_T_CARRY
| TD_SCC_NOTACCESSED
| TD_DP_IN
;
538 for (cnt
= 0; cnt
< urb
->number_of_packets
; cnt
++) {
539 int frame
= urb
->start_frame
;
541 frame
+= cnt
* urb
->interval
;
543 td_fill(ahcd
, info
| frame
,
544 data
+ urb
->iso_frame_desc
[cnt
].offset
,
545 urb
->iso_frame_desc
[cnt
].length
, urb
, cnt
);
547 admhcd_to_hcd(ahcd
)->self
.bandwidth_isoc_reqs
++;
551 if (urb_priv
->td_cnt
!= cnt
)
552 admhc_err(ahcd
, "bad number of tds created for urb %p\n", urb
);
555 /*-------------------------------------------------------------------------*
556 * Done List handling functions
557 *-------------------------------------------------------------------------*/
559 /* calculate transfer length/status and update the urb */
560 static int td_done(struct admhcd
*ahcd
, struct urb
*urb
, struct td
*td
)
562 struct urb_priv
*urb_priv
= urb
->hcpriv
;
566 int type
= usb_pipetype(urb
->pipe
);
568 int status
= -EINPROGRESS
;
570 info
= hc32_to_cpup(ahcd
, &td
->hwINFO
);
571 tdDBP
= hc32_to_cpup(ahcd
, &td
->hwDBP
);
572 bl
= TD_BL_GET(hc32_to_cpup(ahcd
, &td
->hwCBL
));
573 cc
= TD_CC_GET(info
);
575 /* ISO ... drivers see per-TD length/status */
576 if (type
== PIPE_ISOCHRONOUS
) {
580 /* NOTE: assumes FC in tdINFO == 0, and that
581 * only the first of 0..MAXPSW psws is used.
583 if (info
& TD_CC
) /* hc didn't touch? */
586 if (usb_pipeout(urb
->pipe
))
587 dlen
= urb
->iso_frame_desc
[td
->index
].length
;
589 /* short reads are always OK for ISO */
590 if (cc
== TD_CC_DATAUNDERRUN
)
592 dlen
= tdDBP
- td
->data_dma
+ bl
;
595 urb
->actual_length
+= dlen
;
596 urb
->iso_frame_desc
[td
->index
].actual_length
= dlen
;
597 urb
->iso_frame_desc
[td
->index
].status
= cc_to_error
[cc
];
599 if (cc
!= TD_CC_NOERROR
)
601 "urb %p iso td %p (%d) len %d cc %d\n",
602 urb
, td
, 1 + td
->index
, dlen
, cc
);
604 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
605 * except that "setup" bytes aren't counted and "short" transfers
606 * might not be reported as errors.
609 /* update packet status if needed (short is normally ok) */
610 if (cc
== TD_CC_DATAUNDERRUN
611 && !(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
614 if (cc
!= TD_CC_NOERROR
&& cc
< TD_CC_HCD0
)
615 status
= cc_to_error
[cc
];
618 /* count all non-empty packets except control SETUP packet */
619 if ((type
!= PIPE_CONTROL
|| td
->index
!= 0) && tdDBP
!= 0)
620 urb
->actual_length
+= tdDBP
- td
->data_dma
+ bl
;
622 if (cc
!= TD_CC_NOERROR
&& cc
< TD_CC_HCD0
)
624 "urb %p td %p (%d) cc %d, len=%d/%d\n",
625 urb
, td
, td
->index
, cc
,
627 urb
->transfer_buffer_length
);
630 list_del(&td
->td_list
);
636 /*-------------------------------------------------------------------------*/
638 static void ed_halted(struct admhcd
*ahcd
, struct td
*td
, int cc
)
640 struct urb
*urb
= td
->urb
;
641 struct urb_priv
*urb_priv
= urb
->hcpriv
;
642 struct ed
*ed
= td
->ed
;
643 struct list_head
*tmp
= td
->td_list
.next
;
644 __hc32 toggle
= ed
->hwHeadP
& cpu_to_hc32(ahcd
, ED_C
);
646 admhc_dump_ed(ahcd
, "ed halted", td
->ed
, 1);
647 /* clear ed halt; this is the td that caused it, but keep it inactive
648 * until its urb->complete() has a chance to clean up.
650 ed
->hwINFO
|= cpu_to_hc32(ahcd
, ED_SKIP
);
652 ed
->hwHeadP
&= ~cpu_to_hc32(ahcd
, ED_H
);
654 /* Get rid of all later tds from this urb. We don't have
655 * to be careful: no errors and nothing was transferred.
656 * Also patch the ed so it looks as if those tds completed normally.
658 while (tmp
!= &ed
->td_list
) {
661 next
= list_entry(tmp
, struct td
, td_list
);
662 tmp
= next
->td_list
.next
;
664 if (next
->urb
!= urb
)
667 /* NOTE: if multi-td control DATA segments get supported,
668 * this urb had one of them, this td wasn't the last td
669 * in that segment (TD_R clear), this ed halted because
670 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
671 * then we need to leave the control STATUS packet queued
674 list_del(&next
->td_list
);
676 ed
->hwHeadP
= next
->hwNextTD
| toggle
;
679 /* help for troubleshooting: report anything that
680 * looks odd ... that doesn't include protocol stalls
681 * (or maybe some other things)
684 case TD_CC_DATAUNDERRUN
:
685 if ((urb
->transfer_flags
& URB_SHORT_NOT_OK
) == 0)
689 if (usb_pipecontrol(urb
->pipe
))
694 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
695 urb
, urb
->dev
->devpath
,
696 usb_pipeendpoint (urb
->pipe
),
697 usb_pipein(urb
->pipe
) ? "in" : "out",
698 hc32_to_cpu(ahcd
, td
->hwINFO
),
699 cc
, cc_to_error
[cc
]);
703 /*-------------------------------------------------------------------------*/
705 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
707 finish_unlinks(struct admhcd
*ahcd
, u16 tick
)
709 struct ed
*ed
, **last
;
712 for (last
= &ahcd
->ed_rm_list
, ed
= *last
; ed
!= NULL
; ed
= *last
) {
713 struct list_head
*entry
, *tmp
;
714 int completed
, modified
;
717 /* only take off EDs that the HC isn't using, accounting for
718 * frame counter wraps and EDs with partially retired TDs
720 if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd
)->state
))) {
721 if (tick_before(tick
, ed
->tick
)) {
723 last
= &ed
->ed_rm_next
;
727 if (!list_empty(&ed
->td_list
)) {
731 td
= list_entry(ed
->td_list
.next
, struct td
,
733 head
= hc32_to_cpu(ahcd
, ed
->hwHeadP
) &
736 /* INTR_WDH may need to clean up first */
737 if (td
->td_dma
!= head
)
743 /* reentrancy: if we drop the schedule lock, someone might
744 * have modified this list. normally it's just prepending
745 * entries (which we'd ignore), but paranoia won't hurt.
747 *last
= ed
->ed_rm_next
;
748 ed
->ed_rm_next
= NULL
;
751 /* unlink urbs as requested, but rescan the list after
752 * we call a completion since it might have unlinked
753 * another (earlier) urb
755 * When we get here, the HC doesn't see this ed. But it
756 * must not be rescheduled until all completed URBs have
757 * been given back to the driver.
762 list_for_each_safe(entry
, tmp
, &ed
->td_list
) {
765 struct urb_priv
*urb_priv
;
770 td
= list_entry(entry
, struct td
, td_list
);
772 urb_priv
= td
->urb
->hcpriv
;
774 if (!urb
->unlinked
) {
775 prev
= &td
->hwNextTD
;
779 if ((urb_priv
) == NULL
)
782 /* patch pointer hc uses */
783 savebits
= *prev
& ~cpu_to_hc32(ahcd
, TD_MASK
);
784 *prev
= td
->hwNextTD
| savebits
;
785 /* If this was unlinked, the TD may not have been
786 * retired ... so manually save dhe data toggle.
787 * The controller ignores the value we save for
788 * control and ISO endpoints.
790 tdINFO
= hc32_to_cpup(ahcd
, &td
->hwINFO
);
791 if ((tdINFO
& TD_T
) == TD_T_DATA0
)
792 ed
->hwHeadP
&= ~cpu_to_hc32(ahcd
, ED_C
);
793 else if ((tdINFO
& TD_T
) == TD_T_DATA1
)
794 ed
->hwHeadP
|= cpu_to_hc32(ahcd
, ED_C
);
796 /* HC may have partly processed this TD */
797 #ifdef ADMHC_VERBOSE_DEBUG
798 urb_print(ahcd
, urb
, "PARTIAL", 0);
800 status
= td_done(ahcd
, urb
, td
);
802 /* if URB is done, clean up */
803 if (urb_priv
->td_idx
== urb_priv
->td_cnt
) {
804 modified
= completed
= 1;
805 finish_urb(ahcd
, urb
, status
);
808 if (completed
&& !list_empty(&ed
->td_list
))
811 /* ED's now officially unlinked, hc doesn't see */
813 ed
->hwHeadP
&= ~cpu_to_hc32(ahcd
, ED_H
);
816 ed
->hwINFO
&= ~cpu_to_hc32(ahcd
, ED_SKIP
| ED_DEQUEUE
);
818 /* but if there's work queued, reschedule */
819 if (!list_empty(&ed
->td_list
)) {
820 if (HC_IS_RUNNING(admhcd_to_hcd(ahcd
)->state
))
821 ed_schedule(ahcd
, ed
);
829 /*-------------------------------------------------------------------------*/
831 * Process normal completions (error or success) and clean the schedules.
833 * This is the main path for handing urbs back to drivers. The only other
834 * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
835 * instead of scanning the (re-reversed) donelist as this does.
838 static void ed_unhalt(struct admhcd
*ahcd
, struct ed
*ed
, struct urb
*urb
)
840 struct list_head
*entry
, *tmp
;
841 __hc32 toggle
= ed
->hwHeadP
& cpu_to_hc32(ahcd
, ED_C
);
843 #ifdef ADMHC_VERBOSE_DEBUG
844 admhc_dump_ed(ahcd
, "UNHALT", ed
, 0);
846 /* clear ed halt; this is the td that caused it, but keep it inactive
847 * until its urb->complete() has a chance to clean up.
849 ed
->hwINFO
|= cpu_to_hc32(ahcd
, ED_SKIP
);
851 ed
->hwHeadP
&= ~cpu_to_hc32(ahcd
, ED_H
);
853 list_for_each_safe(entry
, tmp
, &ed
->td_list
) {
854 struct td
*td
= list_entry(entry
, struct td
, td_list
);
861 info
&= ~cpu_to_hc32(ahcd
, TD_CC
| TD_OWN
);
864 ed
->hwHeadP
= td
->hwNextTD
| toggle
;
870 static void ed_intr_refill(struct admhcd
*ahcd
, struct ed
*ed
)
872 __hc32 toggle
= ed
->hwHeadP
& cpu_to_hc32(ahcd
, ED_C
);
874 ed
->hwHeadP
= ed
->hwTailP
| toggle
;
878 static inline int is_ed_halted(struct admhcd
*ahcd
, struct ed
*ed
)
880 return ((hc32_to_cpup(ahcd
, &ed
->hwHeadP
) & ED_H
) == ED_H
);
883 static inline int is_td_halted(struct admhcd
*ahcd
, struct ed
*ed
,
886 return ((hc32_to_cpup(ahcd
, &ed
->hwHeadP
) & TD_MASK
) ==
887 (hc32_to_cpup(ahcd
, &td
->hwNextTD
) & TD_MASK
));
890 static void ed_update(struct admhcd
*ahcd
, struct ed
*ed
)
892 struct list_head
*entry
, *tmp
;
894 #ifdef ADMHC_VERBOSE_DEBUG
895 admhc_dump_ed(ahcd
, "UPDATE", ed
, 1);
898 list_for_each_safe(entry
, tmp
, &ed
->td_list
) {
899 struct td
*td
= list_entry(entry
, struct td
, td_list
);
900 struct urb
*urb
= td
->urb
;
901 struct urb_priv
*urb_priv
= urb
->hcpriv
;
904 if (hc32_to_cpup(ahcd
, &td
->hwINFO
) & TD_OWN
)
907 /* update URB's length and status from TD */
908 status
= td_done(ahcd
, urb
, td
);
909 if (is_ed_halted(ahcd
, ed
) && is_td_halted(ahcd
, ed
, td
))
910 ed_unhalt(ahcd
, ed
, urb
);
912 if (ed
->type
== PIPE_INTERRUPT
)
913 ed_intr_refill(ahcd
, ed
);
915 /* If all this urb's TDs are done, call complete() */
916 if (urb_priv
->td_idx
== urb_priv
->td_cnt
)
917 finish_urb(ahcd
, urb
, status
);
919 /* clean schedule: unlink EDs that are no longer busy */
920 if (list_empty(&ed
->td_list
)) {
921 if (ed
->state
== ED_OPER
)
922 start_ed_unlink(ahcd
, ed
);
924 /* ... reenabling halted EDs only after fault cleanup */
925 } else if ((ed
->hwINFO
& cpu_to_hc32(ahcd
,
926 ED_SKIP
| ED_DEQUEUE
))
927 == cpu_to_hc32(ahcd
, ED_SKIP
)) {
928 td
= list_entry(ed
->td_list
.next
, struct td
, td_list
);
930 if (!(td
->hwINFO
& cpu_to_hc32(ahcd
, TD_DONE
))) {
931 ed
->hwINFO
&= ~cpu_to_hc32(ahcd
, ED_SKIP
);
932 /* ... hc may need waking-up */
935 admhc_writel(ahcd
, OHCI_CLF
,
936 &ahcd
->regs
->cmdstatus
);
939 admhc_writel(ahcd
, OHCI_BLF
,
940 &ahcd
->regs
->cmdstatus
);
945 if ((td
->hwINFO
& cpu_to_hc32(ahcd
, TD_OWN
)))
946 ed
->hwINFO
&= ~cpu_to_hc32(ahcd
, ED_SKIP
);
953 /* there are some tds completed; called in_irq(), with HCD locked */
954 static void admhc_td_complete(struct admhcd
*ahcd
)
958 for (ed
= ahcd
->ed_head
; ed
; ed
= ed
->ed_next
) {
959 if (ed
->state
!= ED_OPER
)