1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/delay.h>
4 #include <linux/clk-provider.h>
6 #include <linux/of_address.h>
7 #include <linux/of_device.h>
8 #include <linux/platform_device.h>
9 #include <dt-bindings/clock/en7523-clk.h>
11 #define REG_PCI_CONTROL 0x88
12 #define REG_PCI_CONTROL_PERSTOUT BIT(29)
13 #define REG_PCI_CONTROL_PERSTOUT1 BIT(26)
14 #define REG_PCI_CONTROL_REFCLK_EN1 BIT(22)
15 #define REG_GSW_CLK_DIV_SEL 0x1b4
16 #define REG_EMI_CLK_DIV_SEL 0x1b8
17 #define REG_BUS_CLK_DIV_SEL 0x1bc
18 #define REG_SPI_CLK_DIV_SEL 0x1c4
19 #define REG_SPI_CLK_FREQ_SEL 0x1c8
20 #define REG_NPU_CLK_DIV_SEL 0x1fc
21 #define REG_CRYPTO_CLKSRC 0x200
22 #define REG_RESET_CONTROL 0x834
23 #define REG_RESET_CONTROL_PCIEHB BIT(29)
24 #define REG_RESET_CONTROL_PCIE1 BIT(27)
25 #define REG_RESET_CONTROL_PCIE2 BIT(26)
34 const unsigned int *base_values
;
35 unsigned int base_value
;
51 static const u32 gsw_base
[] = { 400000000, 500000000 };
52 static const u32 emi_base
[] = { 333000000, 400000000 };
53 static const u32 bus_base
[] = { 500000000, 540000000 };
54 static const u32 slic_base
[] = { 100000000, 3125000 };
55 static const u32 npu_base
[] = { 333000000, 400000000, 500000000 };
57 static const struct en_clk_desc en7523_base_clks
[] = {
62 .base_reg
= REG_GSW_CLK_DIV_SEL
,
65 .base_values
= gsw_base
,
66 .n_base_values
= ARRAY_SIZE(gsw_base
),
75 .base_reg
= REG_EMI_CLK_DIV_SEL
,
78 .base_values
= emi_base
,
79 .n_base_values
= ARRAY_SIZE(emi_base
),
88 .base_reg
= REG_BUS_CLK_DIV_SEL
,
91 .base_values
= bus_base
,
92 .n_base_values
= ARRAY_SIZE(bus_base
),
98 .id
= EN7523_CLK_SLIC
,
101 .base_reg
= REG_SPI_CLK_FREQ_SEL
,
104 .base_values
= slic_base
,
105 .n_base_values
= ARRAY_SIZE(slic_base
),
107 .div_reg
= REG_SPI_CLK_DIV_SEL
,
113 .id
= EN7523_CLK_SPI
,
116 .base_reg
= REG_SPI_CLK_DIV_SEL
,
118 .base_value
= 400000000,
125 .id
= EN7523_CLK_NPU
,
128 .base_reg
= REG_NPU_CLK_DIV_SEL
,
131 .base_values
= npu_base
,
132 .n_base_values
= ARRAY_SIZE(npu_base
),
138 .id
= EN7523_CLK_CRYPTO
,
141 .base_reg
= REG_CRYPTO_CLKSRC
,
144 .base_values
= emi_base
,
145 .n_base_values
= ARRAY_SIZE(emi_base
),
149 static const struct of_device_id of_match_clk_en7523
[] = {
150 { .compatible
= "airoha,en7523-scu", },
154 static unsigned int en7523_get_base_rate(void __iomem
*base
, unsigned int i
)
156 const struct en_clk_desc
*desc
= &en7523_base_clks
[i
];
159 if (!desc
->base_bits
)
160 return desc
->base_value
;
162 val
= readl(base
+ desc
->base_reg
);
163 val
>>= desc
->base_shift
;
164 val
&= (1 << desc
->base_bits
) - 1;
166 if (val
>= desc
->n_base_values
)
169 return desc
->base_values
[val
];
172 static u32
en7523_get_div(void __iomem
*base
, int i
)
174 const struct en_clk_desc
*desc
= &en7523_base_clks
[i
];
180 reg
= desc
->div_reg
? desc
->div_reg
: desc
->base_reg
;
181 val
= readl(base
+ reg
);
182 val
>>= desc
->div_shift
;
183 val
&= (1 << desc
->div_bits
) - 1;
185 if (!val
&& desc
->div_val0
)
186 return desc
->div_val0
;
188 return (val
+ 1) * desc
->div_step
;
191 static int en7523_pci_is_enabled(struct clk_hw
*hw
)
193 struct en_clk_gate
*cg
= container_of(hw
, struct en_clk_gate
, hw
);
195 return !!(readl(cg
->base
+ REG_PCI_CONTROL
) & REG_PCI_CONTROL_REFCLK_EN1
);
198 static int en7523_pci_prepare(struct clk_hw
*hw
)
200 struct en_clk_gate
*cg
= container_of(hw
, struct en_clk_gate
, hw
);
201 void __iomem
*np_base
= cg
->base
;
204 /* Need to pull device low before reset */
205 val
= readl(np_base
+ REG_PCI_CONTROL
);
206 val
&= ~(REG_PCI_CONTROL_PERSTOUT1
| REG_PCI_CONTROL_PERSTOUT
);
207 writel(val
, np_base
+ REG_PCI_CONTROL
);
208 usleep_range(1000, 2000);
210 /* Enable PCIe port 1 */
211 val
|= REG_PCI_CONTROL_REFCLK_EN1
;
212 writel(val
, np_base
+ REG_PCI_CONTROL
);
213 usleep_range(1000, 2000);
215 /* Reset to default */
216 val
= readl(np_base
+ REG_RESET_CONTROL
);
217 mask
= REG_RESET_CONTROL_PCIE1
| REG_RESET_CONTROL_PCIE2
|
218 REG_RESET_CONTROL_PCIEHB
;
219 writel(val
& ~mask
, np_base
+ REG_RESET_CONTROL
);
220 usleep_range(1000, 2000);
221 writel(val
| mask
, np_base
+ REG_RESET_CONTROL
);
223 writel(val
& ~mask
, np_base
+ REG_RESET_CONTROL
);
224 usleep_range(5000, 10000);
227 mask
= REG_PCI_CONTROL_PERSTOUT1
| REG_PCI_CONTROL_PERSTOUT
;
228 val
= readl(np_base
+ REG_PCI_CONTROL
);
229 writel(val
& ~mask
, np_base
+ REG_PCI_CONTROL
);
230 usleep_range(1000, 2000);
231 writel(val
| mask
, np_base
+ REG_PCI_CONTROL
);
237 static void en7523_pci_unprepare(struct clk_hw
*hw
)
239 struct en_clk_gate
*cg
= container_of(hw
, struct en_clk_gate
, hw
);
240 void __iomem
*np_base
= cg
->base
;
243 val
= readl(np_base
+ REG_PCI_CONTROL
);
244 val
&= ~REG_PCI_CONTROL_REFCLK_EN1
;
245 writel(val
, np_base
+ REG_PCI_CONTROL
);
248 static struct clk_hw
*en7523_register_pcie_clk(struct device
*dev
,
249 void __iomem
*np_base
)
251 static const struct clk_ops pcie_gate_ops
= {
252 .is_enabled
= en7523_pci_is_enabled
,
253 .prepare
= en7523_pci_prepare
,
254 .unprepare
= en7523_pci_unprepare
,
256 struct clk_init_data init
= {
258 .ops
= &pcie_gate_ops
,
260 struct en_clk_gate
*cg
;
262 cg
= devm_kzalloc(dev
, sizeof(*cg
), GFP_KERNEL
);
268 en7523_pci_unprepare(&cg
->hw
);
270 if (clk_hw_register(dev
, &cg
->hw
))
276 static void en7523_register_clocks(struct device
*dev
, struct clk_hw_onecell_data
*clk_data
,
277 void __iomem
*base
, void __iomem
*np_base
)
283 for (i
= 0; i
< ARRAY_SIZE(en7523_base_clks
); i
++) {
284 const struct en_clk_desc
*desc
= &en7523_base_clks
[i
];
286 rate
= en7523_get_base_rate(base
, i
);
287 rate
/= en7523_get_div(base
, i
);
289 hw
= clk_hw_register_fixed_rate(dev
, desc
->name
, NULL
, 0, rate
);
291 pr_err("Failed to register clk %s: %ld\n",
292 desc
->name
, PTR_ERR(hw
));
296 clk_data
->hws
[desc
->id
] = hw
;
299 hw
= en7523_register_pcie_clk(dev
, np_base
);
300 clk_data
->hws
[EN7523_CLK_PCIE
] = hw
;
302 clk_data
->num
= EN7523_NUM_CLOCKS
;
305 static int en7523_clk_probe(struct platform_device
*pdev
)
307 struct device_node
*node
= pdev
->dev
.of_node
;
308 struct clk_hw_onecell_data
*clk_data
;
309 void __iomem
*base
, *np_base
;
312 base
= devm_platform_ioremap_resource(pdev
, 0);
314 return PTR_ERR(base
);
316 np_base
= devm_platform_ioremap_resource(pdev
, 1);
318 return PTR_ERR(np_base
);
320 clk_data
= devm_kzalloc(&pdev
->dev
,
321 struct_size(clk_data
, hws
, EN7523_NUM_CLOCKS
),
326 en7523_register_clocks(&pdev
->dev
, clk_data
, base
, np_base
);
328 r
= of_clk_add_hw_provider(node
, of_clk_hw_onecell_get
, clk_data
);
331 "could not register clock provider: %s: %d\n",
337 static struct platform_driver clk_en7523_drv
= {
338 .probe
= en7523_clk_probe
,
340 .name
= "clk-en7523",
341 .of_match_table
= of_match_clk_en7523
,
342 .suppress_bind_attrs
= true,
346 static int __init
clk_en7523_init(void)
348 return platform_driver_register(&clk_en7523_drv
);
351 arch_initcall(clk_en7523_init
);