1 From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2 Date: Sat, 21 May 2016 22:46:32 +0200
3 Subject: [PATCH v2 00/23] ata: sata_dwc_460ex: make it working again
5 The last approach in the commit 8b3444852a2b ("sata_dwc_460ex: move to generic
6 DMA driver") to switch to generic DMA engine API wasn't tested on bare metal.
7 Besides that we expecting new board support coming with the same SATA IP but
10 This series is targetting the following things:
11 - a few bug fixes to the original driver
12 - a part to fix the DMA engine usage and in particularly dw_dmac driver
13 - move driver to use generic PHY and "dmas" property which leads to update in DTS
15 The driver has been tested myself on Sam460ex and WD MyBookLive (apollo3g)
16 boards. In any case I ask Christian, Måns, and Julian to independently test and
17 provide Tested-by tag or an error report.
19 Series depends on previously published but not yet fully applied series [1].
21 The patches are also available via public branch [2].
23 [1] http://www.spinics.net/lists/dmaengine/msg09250.html
24 [2] https://bitbucket.org/andy-shev/linux/branch/topic%2Fdw%2Fsata
27 - simplify patch 8 (David Laight)
28 - add Tested-by and Acked-by tags
31 ata: sata_dwc_460ex: set dma_boundary to 0x1fff
32 ata: sata_dwc_460ex: burst size must be in items not bytes
33 ata: sata_dwc_460ex: DMA is always a flow controller
34 ata: sata_dwc_460ex: select only core part of DMA driver
35 ata: sata_dwc_460ex: don't call ata_sff_qc_issue() on DMA commands
36 ata: sata_dwc_460ex: correct HOSTDEV{P}_FROM_*() macros
37 ata: sata_dwc_460ex: supply physical address of FIFO to DMA
38 ata: sata_dwc_460ex: switch to new dmaengine_terminate_* API
39 ata: sata_dwc_460ex: use devm_ioremap
40 ata: sata_dwc_460ex: make debug messages neat
41 powerpc/4xx: Device tree update for the 460ex DWC SATA
43 Christian Lamparter (1):
44 ata: sata_dwc_460ex: fix crash on offline links without an attached
48 ata: sata_dwc_460ex: remove incorrect locking
49 ata: sata_dwc_460ex: skip dma setup for non-dma commands
50 ata: sata_dwc_460ex: use "dmas" DT property to find dma channel
51 ata: sata_dwc_460ex: add phy support
52 ata: sata_dwc_460ex: get rid of global data
53 ata: sata_dwc_460ex: remove empty libata callback
54 ata: sata_dwc_460ex: get rid of some pointless casts
55 ata: sata_dwc_460ex: get rid of incorrect cast
56 ata: sata_dwc_460ex: add __iomem to register base pointer
57 ata: sata_dwc_460ex: use readl/writel_relaxed()
58 ata: sata_dwc_460ex: tidy up sata_dwc_clear_dmacr()
60 arch/powerpc/boot/dts/canyonlands.dts | 15 +-
61 drivers/ata/Kconfig | 12 +-
62 drivers/ata/sata_dwc_460ex.c | 552 +++++++++++++++++-----------------
63 3 files changed, 305 insertions(+), 274 deletions(-)
66 drivers/ata/sata_dwc_460ex.c | 552 ++++++++++++++++++++++---------------------
67 1 file changed, 283 insertions(+), 269 deletions(-)
69 --- a/drivers/ata/sata_dwc_460ex.c
70 +++ b/drivers/ata/sata_dwc_460ex.c
72 #include <linux/kernel.h>
73 #include <linux/module.h>
74 #include <linux/device.h>
75 +#include <linux/dmaengine.h>
76 #include <linux/of_address.h>
77 #include <linux/of_irq.h>
78 #include <linux/of_platform.h>
79 #include <linux/platform_device.h>
80 +#include <linux/phy/phy.h>
81 #include <linux/libata.h>
82 #include <linux/slab.h>
85 #include <scsi/scsi_host.h>
86 #include <scsi/scsi_cmnd.h>
88 -/* Supported DMA engine drivers */
89 -#include <linux/platform_data/dma-dw.h>
90 -#include <linux/dma/dw.h>
92 /* These two are defined in "libata.h" */
96 #define DRV_NAME "sata-dwc"
97 #define DRV_VERSION "1.3"
100 -#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (void __iomem *)(a))
104 -#define in_le32(a) __le32_to_cpu(__raw_readl((void __iomem *)(a)))
106 +#define sata_dwc_writel(a, v) writel_relaxed(v, a)
107 +#define sata_dwc_readl(a) readl_relaxed(a)
113 -#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/
114 +#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
117 SATA_DWC_MAX_PORTS = 1,
118 @@ -102,7 +95,7 @@ struct sata_dwc_regs {
119 u32 versionr; /* Version Register */
120 u32 idr; /* ID Register */
121 u32 unimpl[192]; /* Unimplemented */
122 - u32 dmadr[256]; /* FIFO Locations in DMA Mode */
123 + u32 dmadr[256]; /* FIFO Locations in DMA Mode */
127 @@ -146,9 +139,14 @@ struct sata_dwc_device {
128 struct device *dev; /* generic device struct */
129 struct ata_probe_ent *pe; /* ptr to probe-ent */
130 struct ata_host *host;
131 - u8 __iomem *reg_base;
132 - struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */
133 + struct sata_dwc_regs __iomem *sata_dwc_regs; /* DW SATA specific */
134 + u32 sactive_issued;
135 + u32 sactive_queued;
138 +#ifdef CONFIG_SATA_DWC_OLD_DMA
139 struct dw_dma_chip *dma;
143 #define SATA_DWC_QCMD_MAX 32
144 @@ -159,25 +157,19 @@ struct sata_dwc_device_port {
145 int dma_pending[SATA_DWC_QCMD_MAX];
148 - struct dw_dma_slave *dws;
149 struct dma_chan *chan;
150 struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX];
151 u32 dma_interrupt_count;
155 - * Commonly used DWC SATA driver Macros
156 + * Commonly used DWC SATA driver macros
158 -#define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\
159 - (host)->private_data)
160 -#define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\
161 - (ap)->host->private_data)
162 -#define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\
163 - (ap)->private_data)
164 -#define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\
165 - (qc)->ap->host->private_data)
166 -#define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\
168 +#define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data)
169 +#define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data)
170 +#define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data)
171 +#define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data)
172 +#define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev)
175 SATA_DWC_CMD_ISSUED_NOT = 0,
176 @@ -190,21 +182,6 @@ enum {
177 SATA_DWC_DMA_PENDING_RX = 2,
180 -struct sata_dwc_host_priv {
181 - void __iomem *scr_addr_sstatus;
182 - u32 sata_dwc_sactive_issued ;
183 - u32 sata_dwc_sactive_queued ;
186 -static struct sata_dwc_host_priv host_pvt;
188 -static struct dw_dma_slave sata_dwc_dma_dws = {
198 @@ -215,6 +192,93 @@ static void sata_dwc_dma_xfer_complete(s
199 static void sata_dwc_port_stop(struct ata_port *ap);
200 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
202 +#ifdef CONFIG_SATA_DWC_OLD_DMA
204 +#include <linux/platform_data/dma-dw.h>
205 +#include <linux/dma/dw.h>
207 +static struct dw_dma_slave sata_dwc_dma_dws = {
214 +static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
216 + struct dw_dma_slave *dws = &sata_dwc_dma_dws;
218 + if (dws->dma_dev != chan->device->dev)
221 + chan->private = dws;
225 +static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
227 + struct sata_dwc_device *hsdev = hsdevp->hsdev;
228 + struct dw_dma_slave *dws = &sata_dwc_dma_dws;
229 + dma_cap_mask_t mask;
231 + dws->dma_dev = hsdev->dev;
233 + dma_cap_zero(mask);
234 + dma_cap_set(DMA_SLAVE, mask);
236 + /* Acquire DMA channel */
237 + hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
238 + if (!hsdevp->chan) {
239 + dev_err(hsdev->dev, "%s: dma channel unavailable\n",
247 +static int sata_dwc_dma_init_old(struct platform_device *pdev,
248 + struct sata_dwc_device *hsdev)
250 + struct device_node *np = pdev->dev.of_node;
251 + struct resource *res;
253 + hsdev->dma = devm_kzalloc(&pdev->dev, sizeof(*hsdev->dma), GFP_KERNEL);
257 + hsdev->dma->dev = &pdev->dev;
259 + /* Get SATA DMA interrupt number */
260 + hsdev->dma->irq = irq_of_parse_and_map(np, 1);
261 + if (hsdev->dma->irq == NO_IRQ) {
262 + dev_err(&pdev->dev, "no SATA DMA irq\n");
266 + /* Get physical SATA DMA register base address */
267 + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
268 + hsdev->dma->regs = devm_ioremap_resource(&pdev->dev, res);
269 + if (IS_ERR(hsdev->dma->regs)) {
270 + dev_err(&pdev->dev,
271 + "ioremap failed for AHBDMA register address\n");
272 + return PTR_ERR(hsdev->dma->regs);
275 + /* Initialize AHB DMAC */
276 + return dw_dma_probe(hsdev->dma);
279 +static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
284 + dw_dma_remove(hsdev->dma);
289 static const char *get_prot_descript(u8 protocol)
291 switch ((enum ata_tf_protocols)protocol) {
292 @@ -305,21 +369,20 @@ static struct dma_async_tx_descriptor *d
293 struct ata_port *ap = qc->ap;
294 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
295 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
296 - dma_addr_t addr = (dma_addr_t)&hsdev->sata_dwc_regs->dmadr;
297 struct dma_slave_config sconf;
298 struct dma_async_tx_descriptor *desc;
300 if (qc->dma_dir == DMA_DEV_TO_MEM) {
301 - sconf.src_addr = addr;
302 - sconf.device_fc = true;
303 + sconf.src_addr = hsdev->dmadr;
304 + sconf.device_fc = false;
305 } else { /* DMA_MEM_TO_DEV */
306 - sconf.dst_addr = addr;
307 + sconf.dst_addr = hsdev->dmadr;
308 sconf.device_fc = false;
311 sconf.direction = qc->dma_dir;
312 - sconf.src_maxburst = AHB_DMA_BRST_DFLT;
313 - sconf.dst_maxburst = AHB_DMA_BRST_DFLT;
314 + sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
315 + sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
316 sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
317 sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
319 @@ -336,8 +399,8 @@ static struct dma_async_tx_descriptor *d
320 desc->callback = dma_dwc_xfer_done;
321 desc->callback_param = hsdev;
323 - dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pad\n",
324 - __func__, qc->sg, qc->n_elem, &addr);
325 + dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pa\n", __func__,
326 + qc->sg, qc->n_elem, &hsdev->dmadr);
330 @@ -350,48 +413,38 @@ static int sata_dwc_scr_read(struct ata_
334 - *val = in_le32(link->ap->ioaddr.scr_addr + (scr * 4));
335 - dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
336 - __func__, link->ap->print_id, scr, *val);
337 + *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
338 + dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
339 + link->ap->print_id, scr, *val);
344 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
346 - dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
347 - __func__, link->ap->print_id, scr, val);
348 + dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
349 + link->ap->print_id, scr, val);
350 if (scr > SCR_NOTIFICATION) {
351 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
355 - out_le32(link->ap->ioaddr.scr_addr + (scr * 4), val);
356 + sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
361 -static u32 core_scr_read(unsigned int scr)
363 - return in_le32(host_pvt.scr_addr_sstatus + (scr * 4));
366 -static void core_scr_write(unsigned int scr, u32 val)
368 - out_le32(host_pvt.scr_addr_sstatus + (scr * 4), val);
371 -static void clear_serror(void)
372 +static void clear_serror(struct ata_port *ap)
375 - val = core_scr_read(SCR_ERROR);
376 - core_scr_write(SCR_ERROR, val);
377 + sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
378 + sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
381 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
383 - out_le32(&hsdev->sata_dwc_regs->intpr,
384 - in_le32(&hsdev->sata_dwc_regs->intpr));
385 + sata_dwc_writel(&hsdev->sata_dwc_regs->intpr,
386 + sata_dwc_readl(&hsdev->sata_dwc_regs->intpr));
389 static u32 qcmd_tag_to_mask(u8 tag)
390 @@ -412,7 +465,7 @@ static void sata_dwc_error_intr(struct a
392 ata_ehi_clear_desc(ehi);
394 - serror = core_scr_read(SCR_ERROR);
395 + sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
396 status = ap->ops->sff_check_status(ap);
398 tag = ap->link.active_tag;
399 @@ -423,7 +476,7 @@ static void sata_dwc_error_intr(struct a
400 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
402 /* Clear error register and interrupt bit */
405 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
407 /* This is the only error happening now. TODO check for exact error */
408 @@ -462,12 +515,12 @@ static irqreturn_t sata_dwc_isr(int irq,
409 int handled, num_processed, port = 0;
410 uint intpr, sactive, sactive2, tag_mask;
411 struct sata_dwc_device_port *hsdevp;
412 - host_pvt.sata_dwc_sactive_issued = 0;
413 + hsdev->sactive_issued = 0;
415 spin_lock_irqsave(&host->lock, flags);
417 /* Read the interrupt register */
418 - intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
419 + intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
421 ap = host->ports[port];
422 hsdevp = HSDEVP_FROM_AP(ap);
423 @@ -486,12 +539,12 @@ static irqreturn_t sata_dwc_isr(int irq,
424 if (intpr & SATA_DWC_INTPR_NEWFP) {
425 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
427 - tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
428 + tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
429 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
430 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
431 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
433 - host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
434 + hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
436 qc = ata_qc_from_tag(ap, tag);
438 @@ -505,11 +558,11 @@ static irqreturn_t sata_dwc_isr(int irq,
442 - sactive = core_scr_read(SCR_ACTIVE);
443 - tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
444 + sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
445 + tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
447 /* If no sactive issued and tag_mask is zero then this is not NCQ */
448 - if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
449 + if (hsdev->sactive_issued == 0 && tag_mask == 0) {
450 if (ap->link.active_tag == ATA_TAG_POISON)
453 @@ -579,22 +632,19 @@ DRVSTILLBUSY:
456 /* process completed commands */
457 - sactive = core_scr_read(SCR_ACTIVE);
458 - tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
459 + sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
460 + tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
462 - if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
464 + if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
466 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
467 - __func__, sactive, host_pvt.sata_dwc_sactive_issued,
469 + __func__, sactive, hsdev->sactive_issued, tag_mask);
472 - if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
473 - (host_pvt.sata_dwc_sactive_issued)) {
474 + if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
476 - "Bad tag mask? sactive=0x%08x (host_pvt.sata_dwc_sactive_issued)=0x%08x tag_mask=0x%08x\n",
477 - sactive, host_pvt.sata_dwc_sactive_issued, tag_mask);
478 + "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
479 + sactive, hsdev->sactive_issued, tag_mask);
482 /* read just to clear ... not bad if currently still busy */
483 @@ -656,7 +706,7 @@ STILLBUSY:
484 * we were processing --we read status as part of processing a completed
487 - sactive2 = core_scr_read(SCR_ACTIVE);
488 + sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
489 if (sactive2 != sactive) {
491 "More completed - sactive=0x%x sactive2=0x%x\n",
492 @@ -672,15 +722,14 @@ DONE:
493 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
495 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
496 + u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr);
498 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
499 - out_le32(&(hsdev->sata_dwc_regs->dmacr),
500 - SATA_DWC_DMACR_RX_CLEAR(
501 - in_le32(&(hsdev->sata_dwc_regs->dmacr))));
502 + dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr);
503 + sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
504 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
505 - out_le32(&(hsdev->sata_dwc_regs->dmacr),
506 - SATA_DWC_DMACR_TX_CLEAR(
507 - in_le32(&(hsdev->sata_dwc_regs->dmacr))));
508 + dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr);
509 + sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
512 * This should not happen, it indicates the driver is out of
513 @@ -688,10 +737,9 @@ static void sata_dwc_clear_dmacr(struct
516 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
517 - __func__, tag, hsdevp->dma_pending[tag],
518 - in_le32(&hsdev->sata_dwc_regs->dmacr));
519 - out_le32(&(hsdev->sata_dwc_regs->dmacr),
520 - SATA_DWC_DMACR_TXRXCH_CLEAR);
521 + __func__, tag, hsdevp->dma_pending[tag], dmacr);
522 + sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
523 + SATA_DWC_DMACR_TXRXCH_CLEAR);
527 @@ -716,7 +764,7 @@ static void sata_dwc_dma_xfer_complete(s
528 __func__, qc->tag, qc->tf.command,
529 get_dma_dir_descript(qc->dma_dir),
530 get_prot_descript(qc->tf.protocol),
531 - in_le32(&(hsdev->sata_dwc_regs->dmacr)));
532 + sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
536 @@ -725,7 +773,7 @@ static void sata_dwc_dma_xfer_complete(s
538 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
540 - in_le32(&(hsdev->sata_dwc_regs->dmacr)));
541 + sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
544 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
545 @@ -742,8 +790,9 @@ static int sata_dwc_qc_complete(struct a
549 + struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
550 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
551 - host_pvt.sata_dwc_sactive_queued = 0;
552 + hsdev->sactive_queued = 0;
553 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
555 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
556 @@ -756,10 +805,8 @@ static int sata_dwc_qc_complete(struct a
558 /* clear active bit */
559 mask = (~(qcmd_tag_to_mask(tag)));
560 - host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
562 - host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
564 + hsdev->sactive_queued = hsdev->sactive_queued & mask;
565 + hsdev->sactive_issued = hsdev->sactive_issued & mask;
569 @@ -767,54 +814,62 @@ static int sata_dwc_qc_complete(struct a
570 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
572 /* Enable selective interrupts by setting the interrupt maskregister*/
573 - out_le32(&hsdev->sata_dwc_regs->intmr,
574 - SATA_DWC_INTMR_ERRM |
575 - SATA_DWC_INTMR_NEWFPM |
576 - SATA_DWC_INTMR_PMABRTM |
577 - SATA_DWC_INTMR_DMATM);
578 + sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
579 + SATA_DWC_INTMR_ERRM |
580 + SATA_DWC_INTMR_NEWFPM |
581 + SATA_DWC_INTMR_PMABRTM |
582 + SATA_DWC_INTMR_DMATM);
584 * Unmask the error bits that should trigger an error interrupt by
585 * setting the error mask register.
587 - out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
588 + sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
590 dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
591 - __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
592 - in_le32(&hsdev->sata_dwc_regs->errmr));
593 + __func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
594 + sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
597 -static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
598 +static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
600 - struct sata_dwc_device_port *hsdevp = param;
601 - struct dw_dma_slave *dws = hsdevp->dws;
602 + port->cmd_addr = base + 0x00;
603 + port->data_addr = base + 0x00;
605 - if (dws->dma_dev != chan->device->dev)
607 + port->error_addr = base + 0x04;
608 + port->feature_addr = base + 0x04;
610 - chan->private = dws;
613 + port->nsect_addr = base + 0x08;
615 -static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
617 - port->cmd_addr = (void __iomem *)base + 0x00;
618 - port->data_addr = (void __iomem *)base + 0x00;
619 + port->lbal_addr = base + 0x0c;
620 + port->lbam_addr = base + 0x10;
621 + port->lbah_addr = base + 0x14;
623 + port->device_addr = base + 0x18;
624 + port->command_addr = base + 0x1c;
625 + port->status_addr = base + 0x1c;
627 - port->error_addr = (void __iomem *)base + 0x04;
628 - port->feature_addr = (void __iomem *)base + 0x04;
629 + port->altstatus_addr = base + 0x20;
630 + port->ctl_addr = base + 0x20;
633 - port->nsect_addr = (void __iomem *)base + 0x08;
634 +static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
636 + struct sata_dwc_device *hsdev = hsdevp->hsdev;
637 + struct device *dev = hsdev->dev;
639 - port->lbal_addr = (void __iomem *)base + 0x0c;
640 - port->lbam_addr = (void __iomem *)base + 0x10;
641 - port->lbah_addr = (void __iomem *)base + 0x14;
642 +#ifdef CONFIG_SATA_DWC_OLD_DMA
643 + if (!of_find_property(dev->of_node, "dmas", NULL))
644 + return sata_dwc_dma_get_channel_old(hsdevp);
647 - port->device_addr = (void __iomem *)base + 0x18;
648 - port->command_addr = (void __iomem *)base + 0x1c;
649 - port->status_addr = (void __iomem *)base + 0x1c;
650 + hsdevp->chan = dma_request_chan(dev, "sata-dma");
651 + if (IS_ERR(hsdevp->chan)) {
652 + dev_err(dev, "failed to allocate dma channel: %ld\n",
653 + PTR_ERR(hsdevp->chan));
654 + return PTR_ERR(hsdevp->chan);
657 - port->altstatus_addr = (void __iomem *)base + 0x20;
658 - port->ctl_addr = (void __iomem *)base + 0x20;
663 @@ -829,7 +884,6 @@ static int sata_dwc_port_start(struct at
664 struct sata_dwc_device *hsdev;
665 struct sata_dwc_device_port *hsdevp = NULL;
667 - dma_cap_mask_t mask;
670 hsdev = HSDEV_FROM_AP(ap);
671 @@ -853,20 +907,13 @@ static int sata_dwc_port_start(struct at
673 hsdevp->hsdev = hsdev;
675 - hsdevp->dws = &sata_dwc_dma_dws;
676 - hsdevp->dws->dma_dev = hsdev->dev;
678 - dma_cap_zero(mask);
679 - dma_cap_set(DMA_SLAVE, mask);
680 + err = sata_dwc_dma_get_channel(hsdevp);
682 + goto CLEANUP_ALLOC;
684 - /* Acquire DMA channel */
685 - hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
686 - if (!hsdevp->chan) {
687 - dev_err(hsdev->dev, "%s: dma channel unavailable\n",
690 + err = phy_power_on(hsdev->phy);
695 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
696 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
697 @@ -877,18 +924,18 @@ static int sata_dwc_port_start(struct at
698 if (ap->port_no == 0) {
699 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
701 - out_le32(&hsdev->sata_dwc_regs->dmacr,
702 - SATA_DWC_DMACR_TXRXCH_CLEAR);
703 + sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
704 + SATA_DWC_DMACR_TXRXCH_CLEAR);
706 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
708 - out_le32(&hsdev->sata_dwc_regs->dbtsr,
709 - (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
710 - SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
711 + sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
712 + (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
713 + SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
716 /* Clear any error bits before libata starts issuing commands */
719 ap->private_data = hsdevp;
720 dev_dbg(ap->dev, "%s: done\n", __func__);
722 @@ -903,11 +950,13 @@ CLEANUP:
723 static void sata_dwc_port_stop(struct ata_port *ap)
725 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
726 + struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
728 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
730 - dmaengine_terminate_all(hsdevp->chan);
731 + dmaengine_terminate_sync(hsdevp->chan);
732 dma_release_channel(hsdevp->chan);
733 + phy_power_off(hsdev->phy);
736 ap->private_data = NULL;
737 @@ -924,22 +973,20 @@ static void sata_dwc_exec_command_by_tag
738 struct ata_taskfile *tf,
739 u8 tag, u32 cmd_issued)
741 - unsigned long flags;
742 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
744 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
745 ata_get_cmd_descript(tf->command), tag);
747 - spin_lock_irqsave(&ap->host->lock, flags);
748 hsdevp->cmd_issued[tag] = cmd_issued;
749 - spin_unlock_irqrestore(&ap->host->lock, flags);
752 * Clear SError before executing a new command.
753 * sata_dwc_scr_write and read can not be used here. Clearing the PM
754 * managed SError register for the disk needs to be done before the
755 * task file is loaded.
759 ata_sff_exec_command(ap, tf);
762 @@ -992,18 +1039,18 @@ static void sata_dwc_bmdma_start_by_tag(
763 sata_dwc_tf_dump(ap, &qc->tf);
766 - reg = core_scr_read(SCR_ERROR);
767 + sata_dwc_scr_read(&ap->link, SCR_ERROR, ®);
768 if (reg & SATA_DWC_SERROR_ERR_BITS) {
769 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
773 if (dir == DMA_TO_DEVICE)
774 - out_le32(&hsdev->sata_dwc_regs->dmacr,
775 - SATA_DWC_DMACR_TXCHEN);
776 + sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
777 + SATA_DWC_DMACR_TXCHEN);
779 - out_le32(&hsdev->sata_dwc_regs->dmacr,
780 - SATA_DWC_DMACR_RXCHEN);
781 + sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
782 + SATA_DWC_DMACR_RXCHEN);
784 /* Enable AHB DMA transfer on the specified channel */
785 dmaengine_submit(desc);
786 @@ -1025,36 +1072,12 @@ static void sata_dwc_bmdma_start(struct
787 sata_dwc_bmdma_start_by_tag(qc, tag);
791 - * Function : sata_dwc_qc_prep_by_tag
792 - * arguments : ata_queued_cmd *qc, u8 tag
793 - * Return value : None
794 - * qc_prep for a particular queued command based on tag
796 -static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
798 - struct dma_async_tx_descriptor *desc;
799 - struct ata_port *ap = qc->ap;
800 - struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
802 - dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
803 - __func__, ap->port_no, get_dma_dir_descript(qc->dma_dir),
806 - desc = dma_dwc_xfer_setup(qc);
808 - dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns NULL\n",
812 - hsdevp->desc[tag] = desc;
815 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
819 struct ata_port *ap = qc->ap;
820 + struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
823 if (qc->tag > 0 || ap->link.sactive > 1)
824 @@ -1068,47 +1091,33 @@ static unsigned int sata_dwc_qc_issue(st
826 if (!ata_is_ncq(qc->tf.protocol))
828 - sata_dwc_qc_prep_by_tag(qc, tag);
830 + if (ata_is_dma(qc->tf.protocol)) {
831 + hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
832 + if (!hsdevp->desc[tag])
833 + return AC_ERR_SYSTEM;
835 + hsdevp->desc[tag] = NULL;
838 if (ata_is_ncq(qc->tf.protocol)) {
839 - sactive = core_scr_read(SCR_ACTIVE);
840 + sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
841 sactive |= (0x00000001 << tag);
842 - core_scr_write(SCR_ACTIVE, sactive);
843 + sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
846 "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
847 __func__, tag, qc->ap->link.sactive, sactive);
849 ap->ops->sff_tf_load(ap, &qc->tf);
850 - sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
851 + sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
852 SATA_DWC_CMD_ISSUED_PEND);
854 - ata_sff_qc_issue(qc);
855 + return ata_bmdma_qc_issue(qc);
861 - * Function : sata_dwc_qc_prep
862 - * arguments : ata_queued_cmd *qc
863 - * Return value : None
864 - * qc_prep for a particular queued command
867 -static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
869 - if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
874 - dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
875 - __func__, qc->tag, qc->ap->link.active_tag);
881 static void sata_dwc_error_handler(struct ata_port *ap)
883 ata_sff_error_handler(ap);
884 @@ -1125,17 +1134,22 @@ static int sata_dwc_hardreset(struct ata
885 sata_dwc_enable_interrupts(hsdev);
887 /* Reconfigure the DMA control register */
888 - out_le32(&hsdev->sata_dwc_regs->dmacr,
889 - SATA_DWC_DMACR_TXRXCH_CLEAR);
890 + sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
891 + SATA_DWC_DMACR_TXRXCH_CLEAR);
893 /* Reconfigure the DMA Burst Transaction Size register */
894 - out_le32(&hsdev->sata_dwc_regs->dbtsr,
895 - SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
896 - SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
897 + sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
898 + SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
899 + SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
904 +static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
906 + /* SATA DWC is master only */
910 * scsi mid-layer and libata interface structures
912 @@ -1148,7 +1162,13 @@ static struct scsi_host_template sata_dw
914 .sg_tablesize = LIBATA_MAX_PRD,
915 /* .can_queue = ATA_MAX_QUEUE, */
916 - .dma_boundary = ATA_DMA_BOUNDARY,
918 + * Make sure a LLI block is not created that will span 8K max FIS
919 + * boundary. If the block spans such a FIS boundary, there is a chance
920 + * that a DMA burst will cross that boundary -- this results in an
921 + * error in the host controller.
923 + .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */,
926 static struct ata_port_operations sata_dwc_ops = {
927 @@ -1157,7 +1177,6 @@ static struct ata_port_operations sata_d
928 .error_handler = sata_dwc_error_handler,
929 .hardreset = sata_dwc_hardreset,
931 - .qc_prep = sata_dwc_qc_prep,
932 .qc_issue = sata_dwc_qc_issue,
934 .scr_read = sata_dwc_scr_read,
935 @@ -1166,6 +1185,8 @@ static struct ata_port_operations sata_d
936 .port_start = sata_dwc_port_start,
937 .port_stop = sata_dwc_port_stop,
939 + .sff_dev_select = sata_dwc_dev_select,
941 .bmdma_setup = sata_dwc_bmdma_setup,
942 .bmdma_start = sata_dwc_bmdma_start,
944 @@ -1184,13 +1205,14 @@ static int sata_dwc_probe(struct platfor
945 struct sata_dwc_device *hsdev;
947 char *ver = (char *)&versionr;
949 + void __iomem *base;
952 struct ata_host *host;
953 struct ata_port_info pi = sata_dwc_port_info[0];
954 const struct ata_port_info *ppi[] = { &pi, NULL };
955 struct device_node *np = ofdev->dev.of_node;
956 + struct resource *res;
958 /* Allocate DWC SATA device */
959 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
960 @@ -1201,57 +1223,33 @@ static int sata_dwc_probe(struct platfor
961 host->private_data = hsdev;
963 /* Ioremap SATA registers */
964 - base = of_iomap(np, 0);
966 + res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
967 + base = devm_ioremap_resource(&ofdev->dev, res);
968 + if (IS_ERR(base)) {
970 "ioremap failed for SATA register address\n");
972 + return PTR_ERR(base);
974 - hsdev->reg_base = base;
975 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
977 /* Synopsys DWC SATA specific Registers */
978 - hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
979 + hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
980 + hsdev->dmadr = res->start + SATA_DWC_REG_OFFSET + offsetof(struct sata_dwc_regs, dmadr);
983 host->ports[0]->ioaddr.cmd_addr = base;
984 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
985 - host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
986 - sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
987 + sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
989 /* Read the ID and Version Registers */
990 - idr = in_le32(&hsdev->sata_dwc_regs->idr);
991 - versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
992 + idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
993 + versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
994 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
995 idr, ver[0], ver[1], ver[2]);
997 - /* Get SATA DMA interrupt number */
998 - hsdev->dma->irq = irq_of_parse_and_map(np, 1);
999 - if (hsdev->dma->irq == NO_IRQ) {
1000 - dev_err(&ofdev->dev, "no SATA DMA irq\n");
1005 - /* Get physical SATA DMA register base address */
1006 - hsdev->dma->regs = of_iomap(np, 1);
1007 - if (!hsdev->dma->regs) {
1008 - dev_err(&ofdev->dev,
1009 - "ioremap failed for AHBDMA register address\n");
1014 /* Save dev for later use in dev_xxx() routines */
1015 hsdev->dev = &ofdev->dev;
1017 - hsdev->dma->dev = &ofdev->dev;
1019 - /* Initialize AHB DMAC */
1020 - err = dw_dma_probe(hsdev->dma, NULL);
1022 - goto error_dma_iomap;
1024 /* Enable SATA Interrupts */
1025 sata_dwc_enable_interrupts(hsdev);
1027 @@ -1263,6 +1261,25 @@ static int sata_dwc_probe(struct platfor
1031 +#ifdef CONFIG_SATA_DWC_OLD_DMA
1032 + if (!of_find_property(np, "dmas", NULL)) {
1033 + err = sata_dwc_dma_init_old(ofdev, hsdev);
1039 + hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
1040 + if (IS_ERR(hsdev->phy)) {
1041 + err = PTR_ERR(hsdev->phy);
1042 + hsdev->phy = NULL;
1046 + err = phy_init(hsdev->phy);
1051 * Now, register with libATA core, this will also initiate the
1052 * device discovery process, invoking our port_start() handler &
1053 @@ -1276,12 +1293,7 @@ static int sata_dwc_probe(struct platfor
1057 - /* Free SATA DMA resources */
1058 - dw_dma_remove(hsdev->dma);
1060 - iounmap(hsdev->dma->regs);
1063 + phy_exit(hsdev->phy);
1067 @@ -1293,11 +1305,13 @@ static int sata_dwc_remove(struct platfo
1069 ata_host_detach(host);
1071 + phy_exit(hsdev->phy);
1073 +#ifdef CONFIG_SATA_DWC_OLD_DMA
1074 /* Free SATA DMA resources */
1075 - dw_dma_remove(hsdev->dma);
1076 + sata_dwc_dma_exit_old(hsdev);
1079 - iounmap(hsdev->dma->regs);
1080 - iounmap(hsdev->reg_base);
1081 dev_dbg(&ofdev->dev, "done\n");