1 --- a/arch/powerpc/sysdev/ppc4xx_pci.c
2 +++ b/arch/powerpc/sysdev/ppc4xx_pci.c
3 @@ -1066,15 +1066,24 @@ static int __init apm821xx_pciex_init_po
7 - * Do a software reset on PCIe ports.
8 - * This code is to fix the issue that pci drivers doesn't re-assign
9 - * bus number for PCIE devices after Uboot
10 - * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
11 - * PT quad port, SAS LSI 1064E)
12 + * Only reset the PHY when no link is currently established.
13 + * This is for the Atheros PCIe board which has problems to establish
14 + * the link (again) after this PHY reset. All other currently tested
15 + * PCIe boards don't show this problem.
18 - mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
20 + val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
21 + if (!(val & 0x00001000)) {
23 + * Do a software reset on PCIe ports.
24 + * This code is to fix the issue that pci drivers doesn't re-assign
25 + * bus number for PCIE devices after Uboot
26 + * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
27 + * PT quad port, SAS LSI 1064E)
30 + mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
35 val = PTYPE_LEGACY_ENDPOINT << 20;
36 @@ -1091,9 +1100,12 @@ static int __init apm821xx_pciex_init_po
37 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
38 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
40 - mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
42 - mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
43 + val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
44 + if (!(val & 0x00001000)) {
45 + mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
47 + mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
50 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
51 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |