target/linux/ar7/files/arch/mips/ar7/irq.c

   1 /*
   2  * Copyright (C) 2006, 2007 OpenWrt.org
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/irq_cpu.h>
  23 #include <asm/mipsregs.h>
  24 #include <asm/ar7/ar7.h>
  25
  26 #define EXCEPT_OFFSET   0x80
  27 #define PACE_OFFSET     0xA0
  28 #define CHNLS_OFFSET    0x200
  29
  30 #define REG_OFFSET(irq, reg)    ((irq) / 32 * 0x4 + reg * 0x10)
  31 #define SEC_REG_OFFSET(reg)     (EXCEPT_OFFSET + reg * 0x8)
  32 #define SEC_SR_OFFSET           (SEC_REG_OFFSET(0))     /* 0x80 */
  33 #define CR_OFFSET(irq)          (REG_OFFSET(irq, 1))    /* 0x10 */
  34 #define SEC_CR_OFFSET           (SEC_REG_OFFSET(1))     /* 0x88 */
  35 #define ESR_OFFSET(irq)         (REG_OFFSET(irq, 2))    /* 0x20 */
  36 #define SEC_ESR_OFFSET          (SEC_REG_OFFSET(2))     /* 0x90 */
  37 #define ECR_OFFSET(irq)         (REG_OFFSET(irq, 3))    /* 0x30 */
  38 #define SEC_ECR_OFFSET          (SEC_REG_OFFSET(3))     /* 0x98 */
  39 #define PIR_OFFSET              (0x40)
  40 #define MSR_OFFSET              (0x44)
  41 #define PM_OFFSET(irq)          (REG_OFFSET(irq, 5))    /* 0x50 */
  42 #define TM_OFFSET(irq)          (REG_OFFSET(irq, 6))    /* 0x60 */
  43
  44 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
  45
  46 #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
  47
  48 static void ar7_unmask_irq(unsigned int irq_nr);
  49 static void ar7_mask_irq(unsigned int irq_nr);
  50 static void ar7_ack_irq(unsigned int irq_nr);
  51 static void ar7_unmask_sec_irq(unsigned int irq_nr);
  52 static void ar7_mask_sec_irq(unsigned int irq_nr);
  53 static void ar7_ack_sec_irq(unsigned int irq_nr);
  54 static void ar7_cascade(void);
  55 static void ar7_irq_init(int base);
  56 static int ar7_irq_base;
  57
  58 static struct irq_chip ar7_irq_type = {
  59         .name = "AR7",
  60         .unmask = ar7_unmask_irq,
  61         .mask = ar7_mask_irq,
  62         .ack = ar7_ack_irq
  63 };
  64
  65 static struct irq_chip ar7_sec_irq_type = {
  66         .name = "AR7",
  67         .unmask = ar7_unmask_sec_irq,
  68         .mask = ar7_mask_sec_irq,
  69         .ack = ar7_ack_sec_irq,
  70 };
  71
  72 static struct irqaction ar7_cascade_action = {
  73         .handler = no_action,
  74         .name = "AR7 cascade interrupt"
  75 };
  76
  77 static void ar7_unmask_irq(unsigned int irq)
  78 {
  79         writel(1 << ((irq - ar7_irq_base) % 32),
  80                REG(ESR_OFFSET(irq - ar7_irq_base)));
  81 }
  82
  83 static void ar7_mask_irq(unsigned int irq)
  84 {
  85         writel(1 << ((irq - ar7_irq_base) % 32),
  86                REG(ECR_OFFSET(irq - ar7_irq_base)));
  87 }
  88
  89 static void ar7_ack_irq(unsigned int irq)
  90 {
  91         writel(1 << ((irq - ar7_irq_base) % 32),
  92                REG(CR_OFFSET(irq - ar7_irq_base)));
  93 }
  94
  95 static void ar7_unmask_sec_irq(unsigned int irq)
  96 {
  97         writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
  98 }
  99
 100 static void ar7_mask_sec_irq(unsigned int irq)
 101 {
 102         writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
 103 }
 104
 105 static void ar7_ack_sec_irq(unsigned int irq)
 106 {
 107         writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
 108 }
 109
 110 void __init arch_init_irq(void) {
 111         mips_cpu_irq_init();
 112         ar7_irq_init(8);
 113 }
 114
 115 static void __init ar7_irq_init(int base)
 116 {
 117         int i;
 118         /*
 119          * Disable interrupts and clear pending
 120          */
 121         writel(0xffffffff, REG(ECR_OFFSET(0)));
 122         writel(0xff, REG(ECR_OFFSET(32)));
 123         writel(0xffffffff, REG(SEC_ECR_OFFSET));
 124         writel(0xffffffff, REG(CR_OFFSET(0)));
 125         writel(0xff, REG(CR_OFFSET(32)));
 126         writel(0xffffffff, REG(SEC_CR_OFFSET));
 127
 128         ar7_irq_base = base;
 129
 130         for (i = 0; i < 40; i++) {
 131                 writel(i, REG(CHNL_OFFSET(i)));
 132                 /* Primary IRQ's */
 133                 set_irq_chip_and_handler(base + i, &ar7_irq_type,
 134                                          handle_level_irq);
 135                 /* Secondary IRQ's */
 136                 if (i < 32)
 137                         set_irq_chip_and_handler(base + i + 40,
 138                                                  &ar7_sec_irq_type,
 139                                                  handle_level_irq);
 140         }
 141
 142         setup_irq(2, &ar7_cascade_action);
 143         setup_irq(ar7_irq_base, &ar7_cascade_action);
 144         set_c0_status(IE_IRQ0);
 145 }
 146
 147 static void ar7_cascade(void)
 148 {
 149         u32 status;
 150         int i, irq;
 151
 152         /* Primary IRQ's */
 153         irq = readl(REG(PIR_OFFSET)) & 0x3f;
 154         if (irq) {
 155                 do_IRQ(ar7_irq_base + irq);
 156                 return;
 157         }
 158
 159         /* Secondary IRQ's are cascaded through primary '0' */
 160         writel(1, REG(CR_OFFSET(irq)));
 161         status = readl(REG(SEC_SR_OFFSET));
 162         for (i = 0; i < 32; i++) {
 163                 if (status & 1) {
 164                         do_IRQ(ar7_irq_base + i + 40);
 165                         return;
 166                 }
 167                 status >>= 1;
 168         }
 169
 170         spurious_interrupt();
 171 }
 172
 173 asmlinkage void plat_irq_dispatch(void)
 174 {
 175         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 176         if (pending & STATUSF_IP7)              /* cpu timer */
 177                 do_IRQ(7);
 178         else if (pending & STATUSF_IP2)         /* int0 hardware line */
 179                 ar7_cascade();
 180         else
 181                 spurious_interrupt();
 182 }