2 * Copyright (C) 2006, 2007 OpenWrt.org
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 #include <linux/interrupt.h>
22 #include <asm/irq_cpu.h>
23 #include <asm/mipsregs.h>
24 #include <asm/ar7/ar7.h>
26 #define EXCEPT_OFFSET 0x80
27 #define PACE_OFFSET 0xA0
28 #define CHNLS_OFFSET 0x200
30 #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
31 #define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
32 #define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
33 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
34 #define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
35 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
36 #define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
37 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
38 #define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
39 #define PIR_OFFSET (0x40)
40 #define MSR_OFFSET (0x44)
41 #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
42 #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
44 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
46 #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
48 static void ar7_unmask_irq(unsigned int irq_nr
);
49 static void ar7_mask_irq(unsigned int irq_nr
);
50 static void ar7_ack_irq(unsigned int irq_nr
);
51 static void ar7_unmask_sec_irq(unsigned int irq_nr
);
52 static void ar7_mask_sec_irq(unsigned int irq_nr
);
53 static void ar7_ack_sec_irq(unsigned int irq_nr
);
54 static void ar7_cascade(void);
55 static void ar7_irq_init(int base
);
56 static int ar7_irq_base
;
58 static struct irq_chip ar7_irq_type
= {
60 .unmask
= ar7_unmask_irq
,
65 static struct irq_chip ar7_sec_irq_type
= {
67 .unmask
= ar7_unmask_sec_irq
,
68 .mask
= ar7_mask_sec_irq
,
69 .ack
= ar7_ack_sec_irq
,
72 static struct irqaction ar7_cascade_action
= {
75 .name
= "AR7 cascade interrupt"
78 static struct irqaction ar7_sec_cascade_action
= {
80 .name
= "AR7 secondary cascade interrupt"
83 static void ar7_unmask_irq(unsigned int irq
)
85 writel(1 << ((irq
- ar7_irq_base
) % 32),
86 REG(ESR_OFFSET(irq
- ar7_irq_base
)));
89 static void ar7_mask_irq(unsigned int irq
)
91 writel(1 << ((irq
- ar7_irq_base
) % 32),
92 REG(ECR_OFFSET(irq
- ar7_irq_base
)));
95 static void ar7_ack_irq(unsigned int irq
)
97 writel(1 << ((irq
- ar7_irq_base
) % 32),
98 REG(CR_OFFSET(irq
- ar7_irq_base
)));
101 static void ar7_unmask_sec_irq(unsigned int irq
)
103 writel(1 << (irq
- ar7_irq_base
- 40), REG(SEC_ESR_OFFSET
));
106 static void ar7_mask_sec_irq(unsigned int irq
)
108 writel(1 << (irq
- ar7_irq_base
- 40), REG(SEC_ECR_OFFSET
));
111 static void ar7_ack_sec_irq(unsigned int irq
)
113 writel(1 << (irq
- ar7_irq_base
- 40), REG(SEC_CR_OFFSET
));
116 void __init
arch_init_irq(void) {
121 static void __init
ar7_irq_init(int base
)
125 * Disable interrupts and clear pending
127 writel(0xffffffff, REG(ECR_OFFSET(0)));
128 writel(0xff, REG(ECR_OFFSET(32)));
129 writel(0xffffffff, REG(SEC_ECR_OFFSET
));
130 writel(0xffffffff, REG(CR_OFFSET(0)));
131 writel(0xff, REG(CR_OFFSET(32)));
132 writel(0xffffffff, REG(SEC_CR_OFFSET
));
136 for (i
= 0; i
< 40; i
++) {
137 writel(i
, REG(CHNL_OFFSET(i
)));
139 set_irq_chip_and_handler(base
+ i
, &ar7_irq_type
,
141 /* Secondary IRQ's */
143 set_irq_chip_and_handler(base
+ i
+ 40,
148 setup_irq(2, &ar7_cascade_action
);
149 setup_irq(ar7_irq_base
, &ar7_sec_cascade_action
);
150 set_c0_status(IE_IRQ0
);
153 static void ar7_cascade(void)
159 irq
= readl(REG(PIR_OFFSET
)) & 0x3f;
161 do_IRQ(ar7_irq_base
+ irq
);
165 /* Secondary IRQ's are cascaded through primary '0' */
166 writel(1, REG(CR_OFFSET(irq
)));
167 status
= readl(REG(SEC_SR_OFFSET
));
168 for (i
= 0; i
< 32; i
++) {
170 do_IRQ(ar7_irq_base
+ i
+ 40);
176 spurious_interrupt();
179 asmlinkage
void plat_irq_dispatch(void)
181 unsigned int pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
182 if (pending
& STATUSF_IP7
) /* cpu timer */
184 else if (pending
& STATUSF_IP2
) /* int0 hardware line */
187 spurious_interrupt();