target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c

   1 /*
   2  * Copyright (C) 2006, 2007 OpenWrt.org
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #include <linux/types.h>
  20 #include <linux/pci.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/irq.h>
  24 #include <asm/ar7/vlynq.h>
  25
  26 #define VLYNQ_PCI_SLOTS 2
  27
  28 struct vlynq_reg_config {
  29         u32 offset;
  30         u32 value;
  31 };
  32
  33 struct vlynq_pci_config {
  34         u32 chip_id;
  35         char name[32];
  36         struct vlynq_mapping rx_mapping[4];
  37         int irq;
  38         int irq_type;
  39         u32 chip;
  40         u32 class;
  41         int num_regs;
  42         struct vlynq_reg_config regs[10];
  43 };
  44
  45 struct vlynq_pci_private {
  46         u32 latency;
  47         u32 cache_line;
  48         u32 command;
  49         u32 sz_mask;
  50         struct vlynq_pci_config *config;
  51 };
  52
  53 static struct vlynq_pci_config known_devices[] = {
  54         {
  55                 .chip_id = 0x00000009, .name = "TI TNETW1130",
  56                 .rx_mapping = {
  57                         { .size = 0x22000, .offset = 0xf0000000 },
  58                         { .size = 0x40000, .offset = 0xc0000000 },
  59                         { .size = 0x0, .offset = 0x0 },
  60                         { .size = 0x0, .offset = 0x0 },
  61                 },
  62                 .irq = 0, .chip = 0x9066104c,
  63                 .irq_type = IRQ_TYPE_EDGE_RISING,
  64                 .class = PCI_CLASS_NETWORK_OTHER,
  65                 .num_regs = 5,
  66                 .regs = {
  67                         {
  68                                 .offset = 0x790,
  69                                 .value = (0xd0000000 - PHYS_OFFSET)
  70                         },
  71                         {
  72                                 .offset = 0x794,
  73                                 .value = (0xd0000000 - PHYS_OFFSET)
  74                         },
  75                         { .offset = 0x740, .value = 0 },
  76                         { .offset = 0x744, .value = 0x00010000 },
  77                         { .offset = 0x764, .value = 0x00010000 },
  78                 },
  79         },
  80         {
  81                 .chip_id = 0x00000029, .name = "TI TNETW1350",
  82                 .rx_mapping = {
  83                         { .size = 0x100000, .offset = 0x00300000 },
  84                         { .size = 0x80000, .offset = 0x00000000 },
  85                         { .size = 0x0, .offset = 0x0 },
  86                         { .size = 0x0, .offset = 0x0 },
  87                 },
  88                 .irq = 0, .chip = 0x9066104c,
  89                 .irq_type = IRQ_TYPE_EDGE_RISING,
  90                 .class = PCI_CLASS_NETWORK_OTHER,
  91                 .num_regs = 5,
  92                 .regs = {
  93                         {
  94                                 .offset = 0x790,
  95                                 .value = (0x60000000 - PHYS_OFFSET)
  96                         },
  97                         {
  98                                 .offset = 0x794,
  99                                 .value = (0x60000000 - PHYS_OFFSET)
 100                         },
 101                         { .offset = 0x740, .value = 0 },
 102                         { .offset = 0x744, .value = 0x00010000 },
 103                         { .offset = 0x764, .value = 0x00010000 },
 104                 },
 105         },
 106 };
 107
 108 static struct vlynq_device *slots[VLYNQ_PCI_SLOTS] = { NULL, };
 109
 110 static struct resource vlynq_io_resource = {
 111         .start  = 0x00000000,
 112         .end    = 0x00000000,
 113         .name   = "pci IO space",
 114         .flags  = IORESOURCE_IO
 115 };
 116
 117 static struct resource vlynq_mem_resource = {
 118         .start  = 0x00000000,
 119         .end    = 0x00000000,
 120         .name   = "pci memory space",
 121         .flags  = IORESOURCE_MEM
 122 };
 123
 124 static inline u32 vlynq_get_mapped(struct vlynq_device *dev, int res)
 125 {
 126         int i;
 127         struct vlynq_pci_private *priv = dev->priv;
 128         u32 ret = dev->mem_start;
 129         if (!priv->config->rx_mapping[res].size) return 0;
 130         for (i = 0; i < res; i++)
 131                 ret += priv->config->rx_mapping[i].size;
 132
 133         return ret;
 134 }
 135
 136 static inline u32 vlynq_read(u32 val, int size) {
 137         switch (size) {
 138         case 1:
 139                 return *(u8 *)&val;
 140         case 2:
 141                 return *(u16 *)&val;
 142         }
 143         return val;
 144 }
 145
 146 static int vlynq_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
 147 {
 148         struct vlynq_device *dev;
 149         struct vlynq_pci_private *priv;
 150         int resno, slot = PCI_SLOT(devfn);
 151
 152         if ((size == 2) && (where & 1))
 153                 return PCIBIOS_BAD_REGISTER_NUMBER;
 154         else if ((size == 4) && (where & 3))
 155                 return PCIBIOS_BAD_REGISTER_NUMBER;
 156
 157         if (slot >= VLYNQ_PCI_SLOTS)
 158                 return PCIBIOS_DEVICE_NOT_FOUND;
 159
 160         dev = slots[slot];
 161
 162         if (!dev || (PCI_FUNC(devfn) > 0))
 163                 return PCIBIOS_DEVICE_NOT_FOUND;
 164
 165         priv = dev->priv;
 166
 167         switch (where) {
 168         case PCI_VENDOR_ID:
 169                 *val = vlynq_read(priv->config->chip, size);
 170                 break;
 171         case PCI_DEVICE_ID:
 172                 *val = priv->config->chip & 0xffff;
 173         case PCI_COMMAND:
 174                 *val = priv->command;
 175         case PCI_STATUS:
 176 /*              *val = PCI_STATUS_CAP_LIST;*/
 177                 *val = 0;
 178                 break;
 179         case PCI_CLASS_REVISION:
 180                 *val = priv->config->class;
 181                 break;
 182         case PCI_LATENCY_TIMER:
 183                 *val = priv->latency;
 184                 break;
 185         case PCI_HEADER_TYPE:
 186                 *val = PCI_HEADER_TYPE_NORMAL;
 187                 break;
 188         case PCI_CACHE_LINE_SIZE:
 189                 *val = priv->cache_line;
 190                 break;
 191         case PCI_BASE_ADDRESS_0:
 192         case PCI_BASE_ADDRESS_1:
 193         case PCI_BASE_ADDRESS_2:
 194         case PCI_BASE_ADDRESS_3:
 195                 resno = (where - PCI_BASE_ADDRESS_0) >> 2;
 196                 if (priv->sz_mask & (1 << resno)) {
 197                         priv->sz_mask &= ~(1 << resno);
 198                         *val = priv->config->rx_mapping[resno].size;
 199                 } else {
 200                         *val = vlynq_get_mapped(dev, resno);
 201                 }
 202                 break;
 203         case PCI_BASE_ADDRESS_4:
 204         case PCI_BASE_ADDRESS_5:
 205         case PCI_SUBSYSTEM_VENDOR_ID:
 206         case PCI_SUBSYSTEM_ID:
 207         case PCI_ROM_ADDRESS:
 208         case PCI_INTERRUPT_LINE:
 209         case PCI_CARDBUS_CIS:
 210         case PCI_CAPABILITY_LIST:
 211                 *val = 0;
 212                 break;
 213         case PCI_INTERRUPT_PIN:
 214                 *val = 1;
 215                 break;
 216         default:
 217                 printk("%s: Read of unknown register 0x%x (size %d)\n",
 218                        dev->dev.bus_id, where, size);
 219                 return PCIBIOS_BAD_REGISTER_NUMBER;
 220         }
 221         return PCIBIOS_SUCCESSFUL;
 222 }
 223
 224 static int vlynq_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 225 {
 226         struct vlynq_device *dev;
 227         struct vlynq_pci_private *priv;
 228         int resno, slot = PCI_SLOT(devfn);
 229
 230         if ((size == 2) && (where & 1))
 231                 return PCIBIOS_BAD_REGISTER_NUMBER;
 232         else if ((size == 4) && (where & 3))
 233                 return PCIBIOS_BAD_REGISTER_NUMBER;
 234
 235         if (slot >= VLYNQ_PCI_SLOTS)
 236                 return PCIBIOS_DEVICE_NOT_FOUND;
 237
 238         dev = slots[slot];
 239
 240         if (!dev || (PCI_FUNC(devfn) > 0))
 241                 return PCIBIOS_DEVICE_NOT_FOUND;
 242
 243         priv = dev->priv;
 244
 245         switch (where) {
 246         case PCI_VENDOR_ID:
 247         case PCI_DEVICE_ID:
 248         case PCI_STATUS:
 249         case PCI_CLASS_REVISION:
 250         case PCI_HEADER_TYPE:
 251         case PCI_CACHE_LINE_SIZE:
 252         case PCI_SUBSYSTEM_VENDOR_ID:
 253         case PCI_SUBSYSTEM_ID:
 254         case PCI_INTERRUPT_LINE:
 255         case PCI_INTERRUPT_PIN:
 256         case PCI_CARDBUS_CIS:
 257         case PCI_CAPABILITY_LIST:
 258                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 259         case PCI_COMMAND:
 260                 priv->command = val;
 261         case PCI_LATENCY_TIMER:
 262                 priv->latency = val;
 263                 break;
 264         case PCI_BASE_ADDRESS_0:
 265         case PCI_BASE_ADDRESS_1:
 266         case PCI_BASE_ADDRESS_2:
 267         case PCI_BASE_ADDRESS_3:
 268                 if (val == 0xffffffff) {
 269                         resno = (where - PCI_BASE_ADDRESS_0) >> 2;
 270                         priv->sz_mask |= (1 << resno);
 271                         break;
 272                 }
 273         case PCI_BASE_ADDRESS_4:
 274         case PCI_BASE_ADDRESS_5:
 275         case PCI_ROM_ADDRESS:
 276                 break;
 277         default:
 278                 printk("%s: Write to unknown register 0x%x (size %d) value=0x%x\n",
 279                        dev->dev.bus_id, where, size, val);
 280                 return PCIBIOS_BAD_REGISTER_NUMBER;
 281         }
 282         return PCIBIOS_SUCCESSFUL;
 283 }
 284
 285 static struct pci_ops vlynq_pci_ops = {
 286         vlynq_config_read,
 287         vlynq_config_write
 288 };
 289
 290 static struct pci_controller vlynq_controller = {
 291         .pci_ops        = &vlynq_pci_ops,
 292         .io_resource    = &vlynq_io_resource,
 293         .mem_resource   = &vlynq_mem_resource,
 294 };
 295
 296 static int vlynq_pci_probe(struct vlynq_device *dev)
 297 {
 298         int result, i;
 299         u32 chip_id, addr;
 300         struct vlynq_pci_private *priv;
 301         struct vlynq_mapping mapping[4] = { { 0, }, };
 302         struct vlynq_pci_config *config = NULL;
 303
 304         result = vlynq_set_local_irq(dev, 31);
 305         if (result)
 306                 return result;
 307
 308         result = vlynq_set_remote_irq(dev, 30);
 309         if (result)
 310                 return result;
 311
 312         result = vlynq_device_enable(dev);
 313         if (result)
 314                 return result;
 315
 316         chip_id = vlynq_remote_id(dev);
 317         for (i = 0; i < ARRAY_SIZE(known_devices); i++)
 318                 if (chip_id == known_devices[i].chip_id)
 319                         config = &known_devices[i];
 320
 321         if (!config) {
 322                 printk("vlynq-pci: skipping unknown device "
 323                        "%04x:%04x at %s\n", chip_id >> 16,
 324                        chip_id & 0xffff, dev->dev.bus_id);
 325                 result = -ENODEV;
 326                 goto fail;
 327         }
 328
 329         printk("vlynq-pci: attaching device %s at %s\n",
 330                config->name, dev->dev.bus_id);
 331
 332         priv = kmalloc(sizeof(struct vlynq_pci_private), GFP_KERNEL);
 333         if (!priv) {
 334                 printk(KERN_ERR "%s: failed to allocate private data\n",
 335                        dev->dev.bus_id);
 336                 result = -ENOMEM;
 337                 goto fail;
 338         }
 339
 340         memset(priv, 0, sizeof(struct vlynq_pci_private));
 341         priv->latency = 64;
 342         priv->cache_line = 32;
 343         priv->config = config;
 344
 345         mapping[0].offset = ARCH_PFN_OFFSET << PAGE_SHIFT;
 346         mapping[0].size = 0x02000000;
 347         vlynq_set_local_mapping(dev, dev->mem_start, mapping);
 348         vlynq_set_remote_mapping(dev, 0, config->rx_mapping);
 349
 350         set_irq_type(vlynq_virq_to_irq(dev, config->irq), config->irq_type);
 351
 352         addr = (u32)ioremap_nocache(dev->mem_start, 0x10000);
 353         if (!addr) {
 354                 printk(KERN_ERR "%s: failed to remap io memory\n",
 355                        dev->dev.bus_id);
 356                 result = -ENXIO;
 357                 goto fail;
 358         }
 359
 360         for (i = 0; i < config->num_regs; i++)
 361                 iowrite32(config->regs[i].value,
 362                           (u32 *)(addr + config->regs[i].offset));
 363
 364         dev->priv = priv;
 365         for (i = 0; i < VLYNQ_PCI_SLOTS; i++) {
 366                 if (!slots[i]) {
 367                         slots[i] = dev;
 368                         break;
 369                 }
 370         }
 371
 372         return 0;
 373
 374 fail:
 375         vlynq_device_disable(dev);
 376
 377         return result;
 378 }
 379
 380 static int vlynq_pci_remove(struct vlynq_device *dev)
 381 {
 382         int i;
 383         struct vlynq_pci_private *priv = dev->priv;
 384
 385         for (i = 0; i < VLYNQ_PCI_SLOTS; i++)
 386                 if (slots[i] == dev)
 387                         slots[i] = NULL;
 388
 389         vlynq_device_disable(dev);
 390         kfree(priv);
 391
 392         return 0;
 393 }
 394
 395 static struct vlynq_driver vlynq_pci = {
 396         .name = "PCI over VLYNQ emulation",
 397         .probe = vlynq_pci_probe,
 398         .remove = vlynq_pci_remove,
 399 };
 400
 401 int vlynq_pci_init(void)
 402 {
 403         int res;
 404         res = vlynq_register_driver(&vlynq_pci);
 405         if (res)
 406                 return res;
 407
 408         register_pci_controller(&vlynq_controller);
 409
 410         return 0;
 411 }
 412
 413 int pcibios_map_irq(struct pci_dev *pdev, u8 slot, u8 pin)
 414 {
 415         struct vlynq_device *dev;
 416         struct vlynq_pci_private *priv;
 417
 418         dev = slots[slot];
 419
 420         if (!dev)
 421                 return 0;
 422
 423         priv = dev->priv;
 424
 425         return vlynq_virq_to_irq(dev, priv->config->irq);
 426 }
 427
 428 /* Do platform specific device initialization at pci_enable_device() time */
 429 int pcibios_plat_dev_init(struct pci_dev *dev)
 430 {
 431         return 0;
 432 }