target/linux/ar7/files/include/asm-mips/ar7/gpio.h

   1 /*
   2  * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #ifndef __AR7_GPIO_H__
  20 #define __AR7_GPIO_H__
  21 #include <asm/ar7/ar7.h>
  22 #ifndef __AR7_TITAN_H__
  23 #include <asm/ar7/titan.h>
  24 #endif
  25
  26 #define AR7_GPIO_MAX 32
  27 #define TITAN_GPIO_MAX 51
  28
  29 extern int gpio_request(unsigned gpio, const char *label);
  30 extern void gpio_free(unsigned gpio);
  31
  32 /* Common GPIO layer */
  33 static inline int gpio_get_value_ar7(unsigned gpio)
  34 {
  35         void __iomem *gpio_in =
  36                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
  37
  38         return readl(gpio_in) & (1 << gpio);
  39 }
  40
  41 static inline int gpio_get_value_titan(unsigned gpio)
  42 {
  43         void __iomem *gpio_in0 =
  44                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
  45         void __iomem *gpio_in1 =
  46                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_1);
  47
  48         return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
  49 }
  50
  51 static inline int gpio_get_value(unsigned gpio)
  52 {
  53         return ar7_is_titan() ? gpio_get_value_titan(gpio) :
  54                 gpio_get_value_ar7(gpio);
  55 }
  56
  57 static inline void gpio_set_value_ar7(unsigned gpio, int value)
  58 {
  59         void __iomem *gpio_out =
  60                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
  61         unsigned tmp;
  62
  63         tmp = readl(gpio_out) & ~(1 << gpio);
  64         if (value)
  65                 tmp |= 1 << gpio;
  66         writel(tmp, gpio_out);
  67 }
  68
  69 static inline void gpio_set_value_titan(unsigned gpio, int value)
  70 {
  71         void __iomem *gpio_out0 =
  72                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_0);
  73         void __iomem *gpio_out1 =
  74                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_1);
  75         unsigned tmp;
  76
  77         tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
  78         if (value)
  79                 tmp |= 1 << (gpio & 0x1f);
  80         writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
  81 }
  82
  83 static inline void gpio_set_value(unsigned gpio, int value)
  84 {
  85         if (ar7_is_titan())
  86                 gpio_set_value_titan(gpio, value);
  87         else
  88                 gpio_set_value_ar7(gpio, value);
  89 }
  90
  91 static inline int gpio_direction_input_ar7(unsigned gpio)
  92 {
  93         void __iomem *gpio_dir =
  94                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
  95
  96         if (gpio >= AR7_GPIO_MAX)
  97                 return -EINVAL;
  98
  99         writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
 100
 101         return 0;
 102 }
 103
 104 static inline int gpio_direction_input_titan(unsigned gpio)
 105 {
 106         void __iomem *gpio_dir0 =
 107                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
 108         void __iomem *gpio_dir1 =
 109                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
 110
 111         if (gpio >= TITAN_GPIO_MAX)
 112                 return -EINVAL;
 113
 114         writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
 115                 gpio >> 5 ? gpio_dir1 : gpio_dir0);
 116
 117         return 0;
 118 }
 119
 120 static inline int gpio_direction_input(unsigned gpio)
 121 {
 122         return ar7_is_titan() ?  gpio_direction_input_titan(gpio) :
 123                 gpio_direction_input_ar7(gpio);
 124 }
 125
 126 static inline int gpio_direction_output_ar7(unsigned gpio, int value)
 127 {
 128         void __iomem *gpio_dir =
 129                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
 130
 131         if (gpio >= AR7_GPIO_MAX)
 132                 return -EINVAL;
 133
 134         gpio_set_value(gpio, value);
 135         writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
 136
 137         return 0;
 138 }
 139
 140 static inline int gpio_direction_output_titan(unsigned gpio, int value)
 141 {
 142         void __iomem *gpio_dir0 =
 143                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
 144         void __iomem *gpio_dir1 =
 145                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
 146
 147         if (gpio >= TITAN_GPIO_MAX)
 148                 return -EINVAL;
 149
 150         gpio_set_value_titan(gpio, value);
 151         writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
 152                 (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
 153
 154         return 0;
 155 }
 156
 157 static inline int gpio_direction_output(unsigned gpio, int value)
 158 {
 159         return ar7_is_titan() ?  gpio_direction_output_titan(gpio, value) :
 160                 gpio_direction_output_ar7(gpio, value);
 161 }
 162
 163 static inline int gpio_to_irq(unsigned gpio)
 164 {
 165         return -EINVAL;
 166 }
 167
 168 static inline int irq_to_gpio(unsigned irq)
 169 {
 170         return -EINVAL;
 171 }
 172
 173 /* Board specific GPIO functions */
 174 static inline int ar7_gpio_enable_ar7(unsigned gpio)
 175 {
 176         void __iomem *gpio_en =
 177                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
 178
 179         writel(readl(gpio_en) | (1 << gpio), gpio_en);
 180
 181         return 0;
 182 }
 183
 184 static inline int ar7_gpio_enable_titan(unsigned gpio)
 185 {
 186         void __iomem *gpio_en0 =
 187                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
 188         void __iomem *gpio_en1 =
 189                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
 190
 191         writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
 192                 gpio >> 5 ? gpio_en1 : gpio_en0);
 193
 194         return 0;
 195 }
 196
 197 static inline int ar7_gpio_enable(unsigned gpio)
 198 {
 199         return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
 200                 ar7_gpio_enable_ar7(gpio);
 201 }
 202
 203 static inline int ar7_gpio_disable_ar7(unsigned gpio)
 204 {
 205         void __iomem *gpio_en =
 206                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
 207
 208         writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
 209
 210         return 0;
 211 }
 212
 213 static inline int ar7_gpio_disable_titan(unsigned gpio)
 214 {
 215         void __iomem *gpio_en0 =
 216                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
 217         void __iomem *gpio_en1 =
 218                 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
 219
 220         writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
 221                 gpio >> 5 ? gpio_en1 : gpio_en0);
 222
 223         return 0;
 224 }
 225
 226 static inline int ar7_gpio_disable(unsigned gpio)
 227 {
 228         return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
 229                 ar7_gpio_disable_ar7(gpio);
 230 }
 231
 232 static inline int ar7_init_titan_variant( void )
 233 {
 234         /*UINT32 new_val;*/
 235         unsigned new_val;
 236
 237         /* set GPIO 44 - 47 as input */
 238         /*PAL_sysGpioCtrl(const int, GPIO_PIN, GPIO_INPUT_PIN); */
 239         /*define titan_gpio_ctrl in titan.h*/
 240         titan_gpio_ctrl(44, GPIO_PIN, GPIO_INPUT_PIN);
 241         titan_gpio_ctrl(45, GPIO_PIN, GPIO_INPUT_PIN);
 242         titan_gpio_ctrl(46, GPIO_PIN, GPIO_INPUT_PIN);
 243         titan_gpio_ctrl(47, GPIO_PIN, GPIO_INPUT_PIN);
 244
 245         /* read GPIO to get Titan variant type */
 246         /*fix this*/
 247         titan_sysGpioInValue( &new_val, 1 );
 248
 249         new_val >>= 12;
 250         new_val &= 0x0f;
 251
 252         switch ( new_val )
 253         {
 254         case TITAN_CHIP_1050:
 255         case TITAN_CHIP_1055:
 256         case TITAN_CHIP_1056:
 257         case TITAN_CHIP_1060:
 258                 return new_val;
 259
 260         default:
 261                 break;
 262         }
 263         /* In case we get an invalid value, return the default Titan chip */
 264         return TITAN_CHIP_1050;
 265 }
 266
 267 #include <asm-generic/gpio.h>
 268
 269 #endif