2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/etherdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/serial_8250.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
26 static u8 ar71xx_mac_base
[ETH_ALEN
] __initdata
;
29 * OHCI (USB full speed host controller)
31 static struct resource ar71xx_ohci_resources
[] = {
33 .start
= AR71XX_OHCI_BASE
,
34 .end
= AR71XX_OHCI_BASE
+ AR71XX_OHCI_SIZE
- 1,
35 .flags
= IORESOURCE_MEM
,
38 .start
= AR71XX_MISC_IRQ_OHCI
,
39 .end
= AR71XX_MISC_IRQ_OHCI
,
40 .flags
= IORESOURCE_IRQ
,
44 static struct resource ar7240_ohci_resources
[] = {
46 .start
= AR7240_OHCI_BASE
,
47 .end
= AR7240_OHCI_BASE
+ AR7240_OHCI_SIZE
- 1,
48 .flags
= IORESOURCE_MEM
,
51 .start
= AR71XX_CPU_IRQ_USB
,
52 .end
= AR71XX_CPU_IRQ_USB
,
53 .flags
= IORESOURCE_IRQ
,
57 static u64 ar71xx_ohci_dmamask
= DMA_BIT_MASK(32);
58 static struct platform_device ar71xx_ohci_device
= {
59 .name
= "ar71xx-ohci",
61 .resource
= ar71xx_ohci_resources
,
62 .num_resources
= ARRAY_SIZE(ar71xx_ohci_resources
),
64 .dma_mask
= &ar71xx_ohci_dmamask
,
65 .coherent_dma_mask
= DMA_BIT_MASK(32),
70 * EHCI (USB full speed host controller)
72 static struct resource ar71xx_ehci_resources
[] = {
74 .start
= AR71XX_EHCI_BASE
,
75 .end
= AR71XX_EHCI_BASE
+ AR71XX_EHCI_SIZE
- 1,
76 .flags
= IORESOURCE_MEM
,
79 .start
= AR71XX_CPU_IRQ_USB
,
80 .end
= AR71XX_CPU_IRQ_USB
,
81 .flags
= IORESOURCE_IRQ
,
86 static u64 ar71xx_ehci_dmamask
= DMA_BIT_MASK(32);
87 static struct ar71xx_ehci_platform_data ar71xx_ehci_data
;
89 static struct platform_device ar71xx_ehci_device
= {
90 .name
= "ar71xx-ehci",
92 .resource
= ar71xx_ehci_resources
,
93 .num_resources
= ARRAY_SIZE(ar71xx_ehci_resources
),
95 .dma_mask
= &ar71xx_ehci_dmamask
,
96 .coherent_dma_mask
= DMA_BIT_MASK(32),
97 .platform_data
= &ar71xx_ehci_data
,
101 #define AR71XX_USB_RESET_MASK \
102 (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \
103 | RESET_MODULE_USB_OHCI_DLL)
105 #define AR7240_USB_RESET_MASK \
106 (RESET_MODULE_USB_HOST | RESET_MODULE_USB_OHCI_DLL_7240)
108 static void __init
ar71xx_usb_setup(void)
110 ar71xx_device_stop(AR71XX_USB_RESET_MASK
);
112 ar71xx_device_start(AR71XX_USB_RESET_MASK
);
114 /* Turning on the Buff and Desc swap bits */
115 ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG
, 0xf0000);
117 /* WAR for HW bug. Here it adjusts the duration between two SOFS */
118 ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ
, 0x20c00);
123 static void __init
ar7240_usb_setup(void)
125 ar71xx_ohci_device
.resource
= ar7240_ohci_resources
;
127 ar71xx_device_stop(AR7240_USB_RESET_MASK
);
129 ar71xx_device_start(AR7240_USB_RESET_MASK
);
131 /* WAR for HW bug. Here it adjusts the duration between two SOFS */
132 ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ
, 0x3);
135 static void __init
ar91xx_usb_setup(void)
137 ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE
);
140 ar71xx_device_start(RESET_MODULE_USB_HOST
);
143 ar71xx_device_start(RESET_MODULE_USB_PHY
);
147 void __init
ar71xx_add_device_usb(void)
149 switch (ar71xx_soc
) {
150 case AR71XX_SOC_AR7240
:
152 platform_device_register(&ar71xx_ohci_device
);
155 case AR71XX_SOC_AR7130
:
156 case AR71XX_SOC_AR7141
:
157 case AR71XX_SOC_AR7161
:
159 platform_device_register(&ar71xx_ohci_device
);
160 platform_device_register(&ar71xx_ehci_device
);
163 case AR71XX_SOC_AR9130
:
164 case AR71XX_SOC_AR9132
:
166 ar71xx_ehci_data
.is_ar91xx
= 1;
167 platform_device_register(&ar71xx_ehci_device
);
175 static struct resource ar71xx_uart_resources
[] = {
177 .start
= AR71XX_UART_BASE
,
178 .end
= AR71XX_UART_BASE
+ AR71XX_UART_SIZE
- 1,
179 .flags
= IORESOURCE_MEM
,
183 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
184 static struct plat_serial8250_port ar71xx_uart_data
[] = {
186 .mapbase
= AR71XX_UART_BASE
,
187 .irq
= AR71XX_MISC_IRQ_UART
,
188 .flags
= AR71XX_UART_FLAGS
,
189 .iotype
= UPIO_MEM32
,
192 /* terminating entry */
196 static struct platform_device ar71xx_uart_device
= {
197 .name
= "serial8250",
198 .id
= PLAT8250_DEV_PLATFORM
,
199 .resource
= ar71xx_uart_resources
,
200 .num_resources
= ARRAY_SIZE(ar71xx_uart_resources
),
202 .platform_data
= ar71xx_uart_data
206 void __init
ar71xx_add_device_uart(void)
208 ar71xx_uart_data
[0].uartclk
= ar71xx_ahb_freq
;
209 platform_device_register(&ar71xx_uart_device
);
212 static struct resource ar71xx_mdio_resources
[] = {
215 .flags
= IORESOURCE_MEM
,
216 .start
= AR71XX_GE0_BASE
,
217 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
221 static struct ag71xx_mdio_platform_data ar71xx_mdio_data
;
223 static struct platform_device ar71xx_mdio_device
= {
224 .name
= "ag71xx-mdio",
226 .resource
= ar71xx_mdio_resources
,
227 .num_resources
= ARRAY_SIZE(ar71xx_mdio_resources
),
229 .platform_data
= &ar71xx_mdio_data
,
233 void __init
ar71xx_add_device_mdio(u32 phy_mask
)
235 if (ar71xx_soc
== AR71XX_SOC_AR7240
)
236 ar71xx_mdio_data
.is_ar7240
= 1;
238 ar71xx_mdio_data
.phy_mask
= phy_mask
;
240 platform_device_register(&ar71xx_mdio_device
);
243 static void ar71xx_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
248 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
250 t
= __raw_readl(base
+ cfg_reg
);
253 __raw_writel(t
, base
+ cfg_reg
);
256 __raw_writel(pll_val
, base
+ pll_reg
);
259 __raw_writel(t
, base
+ cfg_reg
);
263 __raw_writel(t
, base
+ cfg_reg
);
266 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
267 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
272 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data
;
273 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data
;
275 static u32
ar71xx_get_eth_pll(unsigned int mac
, int speed
)
277 struct ar71xx_eth_pll_data
*pll_data
;
282 pll_data
= &ar71xx_eth0_pll_data
;
285 pll_data
= &ar71xx_eth1_pll_data
;
293 pll_val
= pll_data
->pll_10
;
296 pll_val
= pll_data
->pll_100
;
299 pll_val
= pll_data
->pll_1000
;
308 static void ar71xx_set_pll_ge0(int speed
)
310 u32 val
= ar71xx_get_eth_pll(0, speed
);
312 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
313 val
, AR71XX_ETH0_PLL_SHIFT
);
316 static void ar71xx_set_pll_ge1(int speed
)
318 u32 val
= ar71xx_get_eth_pll(1, speed
);
320 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
321 val
, AR71XX_ETH1_PLL_SHIFT
);
324 static void ar724x_set_pll_ge0(int speed
)
329 static void ar724x_set_pll_ge1(int speed
)
334 static void ar91xx_set_pll_ge0(int speed
)
336 u32 val
= ar71xx_get_eth_pll(0, speed
);
338 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH0_INT_CLOCK
,
339 val
, AR91XX_ETH0_PLL_SHIFT
);
342 static void ar91xx_set_pll_ge1(int speed
)
344 u32 val
= ar71xx_get_eth_pll(1, speed
);
346 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH1_INT_CLOCK
,
347 val
, AR91XX_ETH1_PLL_SHIFT
);
350 static void ar71xx_ddr_flush_ge0(void)
352 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0
);
355 static void ar71xx_ddr_flush_ge1(void)
357 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1
);
360 static void ar724x_ddr_flush_ge0(void)
362 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0
);
365 static void ar724x_ddr_flush_ge1(void)
367 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1
);
370 static void ar91xx_ddr_flush_ge0(void)
372 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0
);
375 static void ar91xx_ddr_flush_ge1(void)
377 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1
);
380 static struct resource ar71xx_eth0_resources
[] = {
383 .flags
= IORESOURCE_MEM
,
384 .start
= AR71XX_GE0_BASE
,
385 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
388 .flags
= IORESOURCE_MEM
,
389 .start
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
,
390 .end
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
+ 3,
393 .flags
= IORESOURCE_IRQ
,
394 .start
= AR71XX_CPU_IRQ_GE0
,
395 .end
= AR71XX_CPU_IRQ_GE0
,
399 struct ag71xx_platform_data ar71xx_eth0_data
= {
400 .reset_bit
= RESET_MODULE_GE0_MAC
,
403 static struct platform_device ar71xx_eth0_device
= {
406 .resource
= ar71xx_eth0_resources
,
407 .num_resources
= ARRAY_SIZE(ar71xx_eth0_resources
),
409 .platform_data
= &ar71xx_eth0_data
,
413 static struct resource ar71xx_eth1_resources
[] = {
416 .flags
= IORESOURCE_MEM
,
417 .start
= AR71XX_GE1_BASE
,
418 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
421 .flags
= IORESOURCE_MEM
,
422 .start
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
,
423 .end
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
+ 3,
426 .flags
= IORESOURCE_IRQ
,
427 .start
= AR71XX_CPU_IRQ_GE1
,
428 .end
= AR71XX_CPU_IRQ_GE1
,
432 struct ag71xx_platform_data ar71xx_eth1_data
= {
433 .reset_bit
= RESET_MODULE_GE1_MAC
,
436 static struct platform_device ar71xx_eth1_device
= {
439 .resource
= ar71xx_eth1_resources
,
440 .num_resources
= ARRAY_SIZE(ar71xx_eth1_resources
),
442 .platform_data
= &ar71xx_eth1_data
,
446 #define AR71XX_PLL_VAL_1000 0x00110000
447 #define AR71XX_PLL_VAL_100 0x00001099
448 #define AR71XX_PLL_VAL_10 0x00991099
450 #define AR724X_PLL_VAL_1000 0x00110000
451 #define AR724X_PLL_VAL_100 0x00001099
452 #define AR724X_PLL_VAL_10 0x00991099
454 #define AR91XX_PLL_VAL_1000 0x1a000000
455 #define AR91XX_PLL_VAL_100 0x13000a44
456 #define AR91XX_PLL_VAL_10 0x00441099
458 static void __init
ar71xx_init_eth_pll_data(unsigned int id
)
460 struct ar71xx_eth_pll_data
*pll_data
;
461 u32 pll_10
, pll_100
, pll_1000
;
465 pll_data
= &ar71xx_eth0_pll_data
;
468 pll_data
= &ar71xx_eth1_pll_data
;
474 switch (ar71xx_soc
) {
475 case AR71XX_SOC_AR7130
:
476 case AR71XX_SOC_AR7141
:
477 case AR71XX_SOC_AR7161
:
478 pll_10
= AR71XX_PLL_VAL_10
;
479 pll_100
= AR71XX_PLL_VAL_100
;
480 pll_1000
= AR71XX_PLL_VAL_1000
;
483 case AR71XX_SOC_AR7240
:
484 pll_10
= AR724X_PLL_VAL_10
;
485 pll_100
= AR724X_PLL_VAL_100
;
486 pll_1000
= AR724X_PLL_VAL_1000
;
489 case AR71XX_SOC_AR9130
:
490 case AR71XX_SOC_AR9132
:
491 pll_10
= AR91XX_PLL_VAL_10
;
492 pll_100
= AR91XX_PLL_VAL_100
;
493 pll_1000
= AR91XX_PLL_VAL_1000
;
499 if (!pll_data
->pll_10
)
500 pll_data
->pll_10
= pll_10
;
502 if (!pll_data
->pll_100
)
503 pll_data
->pll_100
= pll_100
;
505 if (!pll_data
->pll_1000
)
506 pll_data
->pll_1000
= pll_1000
;
509 static int ar71xx_eth_instance __initdata
;
510 void __init
ar71xx_add_device_eth(unsigned int id
)
512 struct platform_device
*pdev
;
513 struct ag71xx_platform_data
*pdata
;
515 ar71xx_init_eth_pll_data(id
);
519 switch (ar71xx_eth0_data
.phy_if_mode
) {
520 case PHY_INTERFACE_MODE_MII
:
521 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_MII
;
523 case PHY_INTERFACE_MODE_GMII
:
524 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_GMII
;
526 case PHY_INTERFACE_MODE_RGMII
:
527 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RGMII
;
529 case PHY_INTERFACE_MODE_RMII
:
530 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RMII
;
533 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
537 pdev
= &ar71xx_eth0_device
;
540 switch (ar71xx_eth1_data
.phy_if_mode
) {
541 case PHY_INTERFACE_MODE_RMII
:
542 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RMII
;
544 case PHY_INTERFACE_MODE_RGMII
:
545 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RGMII
;
548 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
552 pdev
= &ar71xx_eth1_device
;
555 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
559 pdata
= pdev
->dev
.platform_data
;
561 switch (ar71xx_soc
) {
562 case AR71XX_SOC_AR7130
:
563 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
564 : ar71xx_ddr_flush_ge0
;
565 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
566 : ar71xx_set_pll_ge0
;
569 case AR71XX_SOC_AR7141
:
570 case AR71XX_SOC_AR7161
:
571 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
572 : ar71xx_ddr_flush_ge0
;
573 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
574 : ar71xx_set_pll_ge0
;
578 case AR71XX_SOC_AR7240
:
579 pdata
->ddr_flush
= id
? ar724x_ddr_flush_ge1
580 : ar724x_ddr_flush_ge0
;
581 pdata
->set_pll
= id
? ar724x_set_pll_ge1
582 : ar724x_set_pll_ge0
;
583 pdata
->is_ar724x
= 1;
586 case AR71XX_SOC_AR9130
:
587 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
588 : ar91xx_ddr_flush_ge0
;
589 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
590 : ar91xx_set_pll_ge0
;
591 pdata
->is_ar91xx
= 1;
594 case AR71XX_SOC_AR9132
:
595 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
596 : ar91xx_ddr_flush_ge0
;
597 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
598 : ar91xx_set_pll_ge0
;
599 pdata
->is_ar91xx
= 1;
607 switch (pdata
->phy_if_mode
) {
608 case PHY_INTERFACE_MODE_GMII
:
609 case PHY_INTERFACE_MODE_RGMII
:
610 if (!pdata
->has_gbit
) {
611 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
620 if (is_valid_ether_addr(ar71xx_mac_base
)) {
621 memcpy(pdata
->mac_addr
, ar71xx_mac_base
, ETH_ALEN
);
622 pdata
->mac_addr
[5] += ar71xx_eth_instance
;
624 random_ether_addr(pdata
->mac_addr
);
626 "ar71xx: using random MAC address for eth%d\n",
627 ar71xx_eth_instance
);
630 if (pdata
->mii_bus_dev
== NULL
)
631 pdata
->mii_bus_dev
= &ar71xx_mdio_device
.dev
;
633 /* Reset the device */
634 ar71xx_device_stop(pdata
->reset_bit
);
637 ar71xx_device_start(pdata
->reset_bit
);
640 platform_device_register(pdev
);
641 ar71xx_eth_instance
++;
644 static struct resource ar71xx_spi_resources
[] = {
646 .start
= AR71XX_SPI_BASE
,
647 .end
= AR71XX_SPI_BASE
+ AR71XX_SPI_SIZE
- 1,
648 .flags
= IORESOURCE_MEM
,
652 static struct platform_device ar71xx_spi_device
= {
653 .name
= "ar71xx-spi",
655 .resource
= ar71xx_spi_resources
,
656 .num_resources
= ARRAY_SIZE(ar71xx_spi_resources
),
659 void __init
ar71xx_add_device_spi(struct ar71xx_spi_platform_data
*pdata
,
660 struct spi_board_info
const *info
,
663 spi_register_board_info(info
, n
);
664 ar71xx_spi_device
.dev
.platform_data
= pdata
;
665 platform_device_register(&ar71xx_spi_device
);
668 void __init
ar71xx_add_device_leds_gpio(int id
, unsigned num_leds
,
669 struct gpio_led
*leds
)
671 struct platform_device
*pdev
;
672 struct gpio_led_platform_data pdata
;
676 p
= kmalloc(num_leds
* sizeof(*p
), GFP_KERNEL
);
680 memcpy(p
, leds
, num_leds
* sizeof(*p
));
682 pdev
= platform_device_alloc("leds-gpio", id
);
686 memset(&pdata
, 0, sizeof(pdata
));
687 pdata
.num_leds
= num_leds
;
690 err
= platform_device_add_data(pdev
, &pdata
, sizeof(pdata
));
694 err
= platform_device_add(pdev
);
701 platform_device_put(pdev
);
707 void __init
ar71xx_add_device_gpio_buttons(int id
,
708 unsigned poll_interval
,
710 struct gpio_button
*buttons
)
712 struct platform_device
*pdev
;
713 struct gpio_buttons_platform_data pdata
;
714 struct gpio_button
*p
;
717 p
= kmalloc(nbuttons
* sizeof(*p
), GFP_KERNEL
);
721 memcpy(p
, buttons
, nbuttons
* sizeof(*p
));
723 pdev
= platform_device_alloc("gpio-buttons", id
);
725 goto err_free_buttons
;
727 memset(&pdata
, 0, sizeof(pdata
));
728 pdata
.poll_interval
= poll_interval
;
729 pdata
.nbuttons
= nbuttons
;
732 err
= platform_device_add_data(pdev
, &pdata
, sizeof(pdata
));
737 err
= platform_device_add(pdev
);
744 platform_device_put(pdev
);
750 void __init
ar71xx_add_device_wdt(void)
752 platform_device_register_simple("ar71xx-wdt", -1, NULL
, 0);
755 void __init
ar71xx_set_mac_base(unsigned char *mac
)
757 memcpy(ar71xx_mac_base
, mac
, ETH_ALEN
);
760 void __init
ar71xx_parse_mac_addr(char *mac_str
)
765 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
766 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
769 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
770 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
773 ar71xx_set_mac_base(tmp
);
775 printk(KERN_DEBUG
"ar71xx: failed to parse mac address "
776 "\"%s\"\n", mac_str
);
779 static struct platform_device ar71xx_dsa_switch_device
= {
784 void __init
ar71xx_add_device_dsa(unsigned int id
,
785 struct dsa_platform_data
*d
)
791 d
->netdev
= &ar71xx_eth0_device
.dev
;
794 d
->netdev
= &ar71xx_eth1_device
.dev
;
798 "ar71xx: invalid ethernet id %d for DSA switch\n",
803 for (i
= 0; i
< d
->nr_chips
; i
++)
804 d
->chip
[i
].mii_bus
= &ar71xx_mdio_device
.dev
;
806 ar71xx_dsa_switch_device
.dev
.platform_data
= d
;
808 platform_device_register(&ar71xx_dsa_switch_device
);