2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/etherdevice.h>
18 #include <linux/platform_device.h>
19 #include <linux/serial_8250.h>
21 #include <asm/mach-ar71xx/ar71xx.h>
25 static u8 ar71xx_mac_base
[ETH_ALEN
] __initdata
;
27 static struct resource ar71xx_uart_resources
[] = {
29 .start
= AR71XX_UART_BASE
,
30 .end
= AR71XX_UART_BASE
+ AR71XX_UART_SIZE
- 1,
31 .flags
= IORESOURCE_MEM
,
35 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
36 static struct plat_serial8250_port ar71xx_uart_data
[] = {
38 .mapbase
= AR71XX_UART_BASE
,
39 .irq
= AR71XX_MISC_IRQ_UART
,
40 .flags
= AR71XX_UART_FLAGS
,
44 /* terminating entry */
48 static struct platform_device ar71xx_uart_device
= {
50 .id
= PLAT8250_DEV_PLATFORM
,
51 .resource
= ar71xx_uart_resources
,
52 .num_resources
= ARRAY_SIZE(ar71xx_uart_resources
),
54 .platform_data
= ar71xx_uart_data
58 void __init
ar71xx_add_device_uart(void)
60 ar71xx_uart_data
[0].uartclk
= ar71xx_ahb_freq
;
61 platform_device_register(&ar71xx_uart_device
);
64 static struct resource ar71xx_mdio_resources
[] = {
67 .flags
= IORESOURCE_MEM
,
68 .start
= AR71XX_GE0_BASE
,
69 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
73 static struct ag71xx_mdio_platform_data ar71xx_mdio_data
;
75 struct platform_device ar71xx_mdio_device
= {
76 .name
= "ag71xx-mdio",
78 .resource
= ar71xx_mdio_resources
,
79 .num_resources
= ARRAY_SIZE(ar71xx_mdio_resources
),
81 .platform_data
= &ar71xx_mdio_data
,
85 void __init
ar71xx_add_device_mdio(u32 phy_mask
)
88 case AR71XX_SOC_AR7240
:
89 case AR71XX_SOC_AR7241
:
90 case AR71XX_SOC_AR7242
:
91 ar71xx_mdio_data
.is_ar7240
= 1;
97 ar71xx_mdio_data
.phy_mask
= phy_mask
;
99 platform_device_register(&ar71xx_mdio_device
);
102 static void ar71xx_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
107 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
109 t
= __raw_readl(base
+ cfg_reg
);
112 __raw_writel(t
, base
+ cfg_reg
);
115 __raw_writel(pll_val
, base
+ pll_reg
);
118 __raw_writel(t
, base
+ cfg_reg
);
122 __raw_writel(t
, base
+ cfg_reg
);
125 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
126 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
131 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data
;
132 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data
;
134 static u32
ar71xx_get_eth_pll(unsigned int mac
, int speed
)
136 struct ar71xx_eth_pll_data
*pll_data
;
141 pll_data
= &ar71xx_eth0_pll_data
;
144 pll_data
= &ar71xx_eth1_pll_data
;
152 pll_val
= pll_data
->pll_10
;
155 pll_val
= pll_data
->pll_100
;
158 pll_val
= pll_data
->pll_1000
;
167 static void ar71xx_set_pll_ge0(int speed
)
169 u32 val
= ar71xx_get_eth_pll(0, speed
);
171 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
172 val
, AR71XX_ETH0_PLL_SHIFT
);
175 static void ar71xx_set_pll_ge1(int speed
)
177 u32 val
= ar71xx_get_eth_pll(1, speed
);
179 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
180 val
, AR71XX_ETH1_PLL_SHIFT
);
183 static void ar724x_set_pll_ge0(int speed
)
188 static void ar724x_set_pll_ge1(int speed
)
193 static void ar91xx_set_pll_ge0(int speed
)
195 u32 val
= ar71xx_get_eth_pll(0, speed
);
197 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH0_INT_CLOCK
,
198 val
, AR91XX_ETH0_PLL_SHIFT
);
201 static void ar91xx_set_pll_ge1(int speed
)
203 u32 val
= ar71xx_get_eth_pll(1, speed
);
205 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH1_INT_CLOCK
,
206 val
, AR91XX_ETH1_PLL_SHIFT
);
209 static void ar71xx_ddr_flush_ge0(void)
211 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0
);
214 static void ar71xx_ddr_flush_ge1(void)
216 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1
);
219 static void ar724x_ddr_flush_ge0(void)
221 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0
);
224 static void ar724x_ddr_flush_ge1(void)
226 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1
);
229 static void ar91xx_ddr_flush_ge0(void)
231 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0
);
234 static void ar91xx_ddr_flush_ge1(void)
236 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1
);
239 static struct resource ar71xx_eth0_resources
[] = {
242 .flags
= IORESOURCE_MEM
,
243 .start
= AR71XX_GE0_BASE
,
244 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
247 .flags
= IORESOURCE_MEM
,
248 .start
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
,
249 .end
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
+ 3,
252 .flags
= IORESOURCE_IRQ
,
253 .start
= AR71XX_CPU_IRQ_GE0
,
254 .end
= AR71XX_CPU_IRQ_GE0
,
258 struct ag71xx_platform_data ar71xx_eth0_data
= {
259 .reset_bit
= RESET_MODULE_GE0_MAC
,
262 struct platform_device ar71xx_eth0_device
= {
265 .resource
= ar71xx_eth0_resources
,
266 .num_resources
= ARRAY_SIZE(ar71xx_eth0_resources
),
268 .platform_data
= &ar71xx_eth0_data
,
272 static struct resource ar71xx_eth1_resources
[] = {
275 .flags
= IORESOURCE_MEM
,
276 .start
= AR71XX_GE1_BASE
,
277 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
280 .flags
= IORESOURCE_MEM
,
281 .start
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
,
282 .end
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
+ 3,
285 .flags
= IORESOURCE_IRQ
,
286 .start
= AR71XX_CPU_IRQ_GE1
,
287 .end
= AR71XX_CPU_IRQ_GE1
,
291 struct ag71xx_platform_data ar71xx_eth1_data
= {
292 .reset_bit
= RESET_MODULE_GE1_MAC
,
295 struct platform_device ar71xx_eth1_device
= {
298 .resource
= ar71xx_eth1_resources
,
299 .num_resources
= ARRAY_SIZE(ar71xx_eth1_resources
),
301 .platform_data
= &ar71xx_eth1_data
,
305 #define AR71XX_PLL_VAL_1000 0x00110000
306 #define AR71XX_PLL_VAL_100 0x00001099
307 #define AR71XX_PLL_VAL_10 0x00991099
309 #define AR724X_PLL_VAL_1000 0x00110000
310 #define AR724X_PLL_VAL_100 0x00001099
311 #define AR724X_PLL_VAL_10 0x00991099
313 #define AR91XX_PLL_VAL_1000 0x1a000000
314 #define AR91XX_PLL_VAL_100 0x13000a44
315 #define AR91XX_PLL_VAL_10 0x00441099
317 static void __init
ar71xx_init_eth_pll_data(unsigned int id
)
319 struct ar71xx_eth_pll_data
*pll_data
;
320 u32 pll_10
, pll_100
, pll_1000
;
324 pll_data
= &ar71xx_eth0_pll_data
;
327 pll_data
= &ar71xx_eth1_pll_data
;
333 switch (ar71xx_soc
) {
334 case AR71XX_SOC_AR7130
:
335 case AR71XX_SOC_AR7141
:
336 case AR71XX_SOC_AR7161
:
337 pll_10
= AR71XX_PLL_VAL_10
;
338 pll_100
= AR71XX_PLL_VAL_100
;
339 pll_1000
= AR71XX_PLL_VAL_1000
;
342 case AR71XX_SOC_AR7240
:
343 case AR71XX_SOC_AR7241
:
344 case AR71XX_SOC_AR7242
:
345 pll_10
= AR724X_PLL_VAL_10
;
346 pll_100
= AR724X_PLL_VAL_100
;
347 pll_1000
= AR724X_PLL_VAL_1000
;
350 case AR71XX_SOC_AR9130
:
351 case AR71XX_SOC_AR9132
:
352 pll_10
= AR91XX_PLL_VAL_10
;
353 pll_100
= AR91XX_PLL_VAL_100
;
354 pll_1000
= AR91XX_PLL_VAL_1000
;
360 if (!pll_data
->pll_10
)
361 pll_data
->pll_10
= pll_10
;
363 if (!pll_data
->pll_100
)
364 pll_data
->pll_100
= pll_100
;
366 if (!pll_data
->pll_1000
)
367 pll_data
->pll_1000
= pll_1000
;
370 static int ar71xx_eth_instance __initdata
;
371 void __init
ar71xx_add_device_eth(unsigned int id
)
373 struct platform_device
*pdev
;
374 struct ag71xx_platform_data
*pdata
;
376 ar71xx_init_eth_pll_data(id
);
380 switch (ar71xx_eth0_data
.phy_if_mode
) {
381 case PHY_INTERFACE_MODE_MII
:
382 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_MII
;
384 case PHY_INTERFACE_MODE_GMII
:
385 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_GMII
;
387 case PHY_INTERFACE_MODE_RGMII
:
388 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RGMII
;
390 case PHY_INTERFACE_MODE_RMII
:
391 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RMII
;
394 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
398 pdev
= &ar71xx_eth0_device
;
401 switch (ar71xx_eth1_data
.phy_if_mode
) {
402 case PHY_INTERFACE_MODE_RMII
:
403 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RMII
;
405 case PHY_INTERFACE_MODE_RGMII
:
406 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RGMII
;
409 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
413 pdev
= &ar71xx_eth1_device
;
416 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
420 pdata
= pdev
->dev
.platform_data
;
422 switch (ar71xx_soc
) {
423 case AR71XX_SOC_AR7130
:
424 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
425 : ar71xx_ddr_flush_ge0
;
426 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
427 : ar71xx_set_pll_ge0
;
430 case AR71XX_SOC_AR7141
:
431 case AR71XX_SOC_AR7161
:
432 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
433 : ar71xx_ddr_flush_ge0
;
434 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
435 : ar71xx_set_pll_ge0
;
439 case AR71XX_SOC_AR7240
:
440 case AR71XX_SOC_AR7241
:
441 case AR71XX_SOC_AR7242
:
442 pdata
->ddr_flush
= id
? ar724x_ddr_flush_ge1
443 : ar724x_ddr_flush_ge0
;
444 pdata
->set_pll
= id
? ar724x_set_pll_ge1
445 : ar724x_set_pll_ge0
;
446 pdata
->is_ar724x
= 1;
449 case AR71XX_SOC_AR9130
:
450 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
451 : ar91xx_ddr_flush_ge0
;
452 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
453 : ar91xx_set_pll_ge0
;
454 pdata
->is_ar91xx
= 1;
457 case AR71XX_SOC_AR9132
:
458 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
459 : ar91xx_ddr_flush_ge0
;
460 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
461 : ar91xx_set_pll_ge0
;
462 pdata
->is_ar91xx
= 1;
470 switch (pdata
->phy_if_mode
) {
471 case PHY_INTERFACE_MODE_GMII
:
472 case PHY_INTERFACE_MODE_RGMII
:
473 if (!pdata
->has_gbit
) {
474 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
483 if (is_valid_ether_addr(ar71xx_mac_base
)) {
484 memcpy(pdata
->mac_addr
, ar71xx_mac_base
, ETH_ALEN
);
485 pdata
->mac_addr
[5] += ar71xx_eth_instance
;
487 random_ether_addr(pdata
->mac_addr
);
489 "ar71xx: using random MAC address for eth%d\n",
490 ar71xx_eth_instance
);
493 if (pdata
->mii_bus_dev
== NULL
)
494 pdata
->mii_bus_dev
= &ar71xx_mdio_device
.dev
;
496 /* Reset the device */
497 ar71xx_device_stop(pdata
->reset_bit
);
500 ar71xx_device_start(pdata
->reset_bit
);
503 platform_device_register(pdev
);
504 ar71xx_eth_instance
++;
507 static struct resource ar71xx_spi_resources
[] = {
509 .start
= AR71XX_SPI_BASE
,
510 .end
= AR71XX_SPI_BASE
+ AR71XX_SPI_SIZE
- 1,
511 .flags
= IORESOURCE_MEM
,
515 static struct platform_device ar71xx_spi_device
= {
516 .name
= "ar71xx-spi",
518 .resource
= ar71xx_spi_resources
,
519 .num_resources
= ARRAY_SIZE(ar71xx_spi_resources
),
522 void __init
ar71xx_add_device_spi(struct ar71xx_spi_platform_data
*pdata
,
523 struct spi_board_info
const *info
,
526 spi_register_board_info(info
, n
);
527 ar71xx_spi_device
.dev
.platform_data
= pdata
;
528 platform_device_register(&ar71xx_spi_device
);
531 void __init
ar71xx_add_device_wdt(void)
533 platform_device_register_simple("ar71xx-wdt", -1, NULL
, 0);
536 void __init
ar71xx_set_mac_base(unsigned char *mac
)
538 memcpy(ar71xx_mac_base
, mac
, ETH_ALEN
);
541 void __init
ar71xx_parse_mac_addr(char *mac_str
)
546 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
547 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
550 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
551 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
554 ar71xx_set_mac_base(tmp
);
556 printk(KERN_DEBUG
"ar71xx: failed to parse mac address "
557 "\"%s\"\n", mac_str
);
560 static int __init
ar71xx_ethaddr_setup(char *str
)
562 ar71xx_parse_mac_addr(str
);
565 __setup("ethaddr=", ar71xx_ethaddr_setup
);
567 static int __init
ar71xx_kmac_setup(char *str
)
569 ar71xx_parse_mac_addr(str
);
572 __setup("kmac=", ar71xx_kmac_setup
);