2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach-ar71xx/ar71xx.h>
27 unsigned char ar71xx_mac_base
[ETH_ALEN
] __initdata
;
29 static struct resource ar71xx_uart_resources
[] = {
31 .start
= AR71XX_UART_BASE
,
32 .end
= AR71XX_UART_BASE
+ AR71XX_UART_SIZE
- 1,
33 .flags
= IORESOURCE_MEM
,
37 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
38 static struct plat_serial8250_port ar71xx_uart_data
[] = {
40 .mapbase
= AR71XX_UART_BASE
,
41 .irq
= AR71XX_MISC_IRQ_UART
,
42 .flags
= AR71XX_UART_FLAGS
,
46 /* terminating entry */
50 static struct platform_device ar71xx_uart_device
= {
52 .id
= PLAT8250_DEV_PLATFORM
,
53 .resource
= ar71xx_uart_resources
,
54 .num_resources
= ARRAY_SIZE(ar71xx_uart_resources
),
56 .platform_data
= ar71xx_uart_data
60 void __init
ar71xx_add_device_uart(void)
63 case AR71XX_SOC_AR7130
:
64 case AR71XX_SOC_AR7141
:
65 case AR71XX_SOC_AR7161
:
66 case AR71XX_SOC_AR7240
:
67 case AR71XX_SOC_AR7241
:
68 case AR71XX_SOC_AR7242
:
69 case AR71XX_SOC_AR9130
:
70 case AR71XX_SOC_AR9132
:
71 ar71xx_uart_data
[0].uartclk
= ar71xx_ahb_freq
;
74 case AR71XX_SOC_AR9330
:
75 case AR71XX_SOC_AR9331
:
76 /* These SoCs are using a different UART core */
79 case AR71XX_SOC_AR9341
:
80 case AR71XX_SOC_AR9342
:
81 case AR71XX_SOC_AR9344
:
82 ar71xx_uart_data
[0].uartclk
= ar71xx_ref_freq
;
89 platform_device_register(&ar71xx_uart_device
);
92 static struct resource ar71xx_mdio_resources
[] = {
95 .flags
= IORESOURCE_MEM
,
96 .start
= AR71XX_GE0_BASE
,
97 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
101 static struct ag71xx_mdio_platform_data ar71xx_mdio_data
;
103 struct platform_device ar71xx_mdio_device
= {
104 .name
= "ag71xx-mdio",
106 .resource
= ar71xx_mdio_resources
,
107 .num_resources
= ARRAY_SIZE(ar71xx_mdio_resources
),
109 .platform_data
= &ar71xx_mdio_data
,
113 static void ar71xx_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
118 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
120 t
= __raw_readl(base
+ cfg_reg
);
123 __raw_writel(t
, base
+ cfg_reg
);
126 __raw_writel(pll_val
, base
+ pll_reg
);
129 __raw_writel(t
, base
+ cfg_reg
);
133 __raw_writel(t
, base
+ cfg_reg
);
136 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
137 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
142 void __init
ar71xx_add_device_mdio(u32 phy_mask
)
144 switch (ar71xx_soc
) {
145 case AR71XX_SOC_AR7240
:
146 ar71xx_mdio_data
.is_ar7240
= 1;
148 case AR71XX_SOC_AR7241
:
149 ar71xx_mdio_data
.is_ar7240
= 1;
150 ar71xx_mdio_resources
[0].start
= AR71XX_GE1_BASE
;
151 ar71xx_mdio_resources
[0].end
= AR71XX_GE1_BASE
+ 0x200 - 1;
153 case AR71XX_SOC_AR7242
:
154 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
155 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
156 AR71XX_ETH0_PLL_SHIFT
);
162 ar71xx_mdio_data
.phy_mask
= phy_mask
;
164 platform_device_register(&ar71xx_mdio_device
);
167 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data
;
168 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data
;
170 static u32
ar71xx_get_eth_pll(unsigned int mac
, int speed
)
172 struct ar71xx_eth_pll_data
*pll_data
;
177 pll_data
= &ar71xx_eth0_pll_data
;
180 pll_data
= &ar71xx_eth1_pll_data
;
188 pll_val
= pll_data
->pll_10
;
191 pll_val
= pll_data
->pll_100
;
194 pll_val
= pll_data
->pll_1000
;
203 static void ar71xx_set_pll_ge0(int speed
)
205 u32 val
= ar71xx_get_eth_pll(0, speed
);
207 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
208 val
, AR71XX_ETH0_PLL_SHIFT
);
211 static void ar71xx_set_pll_ge1(int speed
)
213 u32 val
= ar71xx_get_eth_pll(1, speed
);
215 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
216 val
, AR71XX_ETH1_PLL_SHIFT
);
219 static void ar724x_set_pll_ge0(int speed
)
224 static void ar724x_set_pll_ge1(int speed
)
229 static void ar7242_set_pll_ge0(int speed
)
231 u32 val
= ar71xx_get_eth_pll(0, speed
);
233 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR7242_PLL_REG_ETH0_INT_CLOCK
,
234 val
, AR71XX_ETH0_PLL_SHIFT
);
237 static void ar91xx_set_pll_ge0(int speed
)
239 u32 val
= ar71xx_get_eth_pll(0, speed
);
241 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH0_INT_CLOCK
,
242 val
, AR91XX_ETH0_PLL_SHIFT
);
245 static void ar91xx_set_pll_ge1(int speed
)
247 u32 val
= ar71xx_get_eth_pll(1, speed
);
249 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH1_INT_CLOCK
,
250 val
, AR91XX_ETH1_PLL_SHIFT
);
253 static void ar71xx_ddr_flush_ge0(void)
255 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0
);
258 static void ar71xx_ddr_flush_ge1(void)
260 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1
);
263 static void ar724x_ddr_flush_ge0(void)
265 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0
);
268 static void ar724x_ddr_flush_ge1(void)
270 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1
);
273 static void ar91xx_ddr_flush_ge0(void)
275 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0
);
278 static void ar91xx_ddr_flush_ge1(void)
280 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1
);
283 static struct resource ar71xx_eth0_resources
[] = {
286 .flags
= IORESOURCE_MEM
,
287 .start
= AR71XX_GE0_BASE
,
288 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
291 .flags
= IORESOURCE_MEM
,
292 .start
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
,
293 .end
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
+ 3,
296 .flags
= IORESOURCE_IRQ
,
297 .start
= AR71XX_CPU_IRQ_GE0
,
298 .end
= AR71XX_CPU_IRQ_GE0
,
302 struct ag71xx_platform_data ar71xx_eth0_data
= {
303 .reset_bit
= RESET_MODULE_GE0_MAC
,
306 struct platform_device ar71xx_eth0_device
= {
309 .resource
= ar71xx_eth0_resources
,
310 .num_resources
= ARRAY_SIZE(ar71xx_eth0_resources
),
312 .platform_data
= &ar71xx_eth0_data
,
316 static struct resource ar71xx_eth1_resources
[] = {
319 .flags
= IORESOURCE_MEM
,
320 .start
= AR71XX_GE1_BASE
,
321 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
324 .flags
= IORESOURCE_MEM
,
325 .start
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
,
326 .end
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
+ 3,
329 .flags
= IORESOURCE_IRQ
,
330 .start
= AR71XX_CPU_IRQ_GE1
,
331 .end
= AR71XX_CPU_IRQ_GE1
,
335 struct ag71xx_platform_data ar71xx_eth1_data
= {
336 .reset_bit
= RESET_MODULE_GE1_MAC
,
339 struct platform_device ar71xx_eth1_device
= {
342 .resource
= ar71xx_eth1_resources
,
343 .num_resources
= ARRAY_SIZE(ar71xx_eth1_resources
),
345 .platform_data
= &ar71xx_eth1_data
,
349 #define AR71XX_PLL_VAL_1000 0x00110000
350 #define AR71XX_PLL_VAL_100 0x00001099
351 #define AR71XX_PLL_VAL_10 0x00991099
353 #define AR724X_PLL_VAL_1000 0x00110000
354 #define AR724X_PLL_VAL_100 0x00001099
355 #define AR724X_PLL_VAL_10 0x00991099
357 #define AR7242_PLL_VAL_1000 0x1c000000
358 #define AR7242_PLL_VAL_100 0x00000101
359 #define AR7242_PLL_VAL_10 0x00001616
361 #define AR91XX_PLL_VAL_1000 0x1a000000
362 #define AR91XX_PLL_VAL_100 0x13000a44
363 #define AR91XX_PLL_VAL_10 0x00441099
365 static void __init
ar71xx_init_eth_pll_data(unsigned int id
)
367 struct ar71xx_eth_pll_data
*pll_data
;
368 u32 pll_10
, pll_100
, pll_1000
;
372 pll_data
= &ar71xx_eth0_pll_data
;
375 pll_data
= &ar71xx_eth1_pll_data
;
381 switch (ar71xx_soc
) {
382 case AR71XX_SOC_AR7130
:
383 case AR71XX_SOC_AR7141
:
384 case AR71XX_SOC_AR7161
:
385 pll_10
= AR71XX_PLL_VAL_10
;
386 pll_100
= AR71XX_PLL_VAL_100
;
387 pll_1000
= AR71XX_PLL_VAL_1000
;
390 case AR71XX_SOC_AR7240
:
391 case AR71XX_SOC_AR7241
:
392 pll_10
= AR724X_PLL_VAL_10
;
393 pll_100
= AR724X_PLL_VAL_100
;
394 pll_1000
= AR724X_PLL_VAL_1000
;
397 case AR71XX_SOC_AR7242
:
398 pll_10
= AR7242_PLL_VAL_10
;
399 pll_100
= AR7242_PLL_VAL_100
;
400 pll_1000
= AR7242_PLL_VAL_1000
;
403 case AR71XX_SOC_AR9130
:
404 case AR71XX_SOC_AR9132
:
405 pll_10
= AR91XX_PLL_VAL_10
;
406 pll_100
= AR91XX_PLL_VAL_100
;
407 pll_1000
= AR91XX_PLL_VAL_1000
;
413 if (!pll_data
->pll_10
)
414 pll_data
->pll_10
= pll_10
;
416 if (!pll_data
->pll_100
)
417 pll_data
->pll_100
= pll_100
;
419 if (!pll_data
->pll_1000
)
420 pll_data
->pll_1000
= pll_1000
;
423 static int ar71xx_eth_instance __initdata
;
424 void __init
ar71xx_add_device_eth(unsigned int id
)
426 struct platform_device
*pdev
;
427 struct ag71xx_platform_data
*pdata
;
429 ar71xx_init_eth_pll_data(id
);
433 switch (ar71xx_eth0_data
.phy_if_mode
) {
434 case PHY_INTERFACE_MODE_MII
:
435 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_MII
;
437 case PHY_INTERFACE_MODE_GMII
:
438 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_GMII
;
440 case PHY_INTERFACE_MODE_RGMII
:
441 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RGMII
;
443 case PHY_INTERFACE_MODE_RMII
:
444 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RMII
;
447 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
451 pdev
= &ar71xx_eth0_device
;
454 switch (ar71xx_eth1_data
.phy_if_mode
) {
455 case PHY_INTERFACE_MODE_RMII
:
456 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RMII
;
458 case PHY_INTERFACE_MODE_RGMII
:
459 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RGMII
;
462 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
466 pdev
= &ar71xx_eth1_device
;
469 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
473 pdata
= pdev
->dev
.platform_data
;
475 switch (ar71xx_soc
) {
476 case AR71XX_SOC_AR7130
:
477 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
478 : ar71xx_ddr_flush_ge0
;
479 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
480 : ar71xx_set_pll_ge0
;
483 case AR71XX_SOC_AR7141
:
484 case AR71XX_SOC_AR7161
:
485 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
486 : ar71xx_ddr_flush_ge0
;
487 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
488 : ar71xx_set_pll_ge0
;
492 case AR71XX_SOC_AR7242
:
493 ar71xx_eth0_data
.reset_bit
|= AR724X_RESET_GE0_MDIO
;
494 ar71xx_eth1_data
.reset_bit
|= AR724X_RESET_GE1_MDIO
;
495 pdata
->ddr_flush
= id
? ar724x_ddr_flush_ge1
496 : ar724x_ddr_flush_ge0
;
497 pdata
->set_pll
= id
? ar724x_set_pll_ge1
498 : ar7242_set_pll_ge0
;
500 pdata
->is_ar724x
= 1;
502 if (!pdata
->fifo_cfg1
)
503 pdata
->fifo_cfg1
= 0x0010ffff;
504 if (!pdata
->fifo_cfg2
)
505 pdata
->fifo_cfg2
= 0x015500aa;
506 if (!pdata
->fifo_cfg3
)
507 pdata
->fifo_cfg3
= 0x01f00140;
510 case AR71XX_SOC_AR7241
:
511 ar71xx_eth0_data
.reset_bit
|= AR724X_RESET_GE0_MDIO
;
512 ar71xx_eth1_data
.reset_bit
|= AR724X_RESET_GE1_MDIO
;
514 case AR71XX_SOC_AR7240
:
515 pdata
->ddr_flush
= id
? ar724x_ddr_flush_ge1
516 : ar724x_ddr_flush_ge0
;
517 pdata
->set_pll
= id
? ar724x_set_pll_ge1
518 : ar724x_set_pll_ge0
;
519 pdata
->is_ar724x
= 1;
521 if (!pdata
->fifo_cfg1
)
522 pdata
->fifo_cfg1
= 0x0010ffff;
523 if (!pdata
->fifo_cfg2
)
524 pdata
->fifo_cfg2
= 0x015500aa;
525 if (!pdata
->fifo_cfg3
)
526 pdata
->fifo_cfg3
= 0x01f00140;
529 case AR71XX_SOC_AR9130
:
530 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
531 : ar91xx_ddr_flush_ge0
;
532 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
533 : ar91xx_set_pll_ge0
;
534 pdata
->is_ar91xx
= 1;
537 case AR71XX_SOC_AR9132
:
538 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
539 : ar91xx_ddr_flush_ge0
;
540 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
541 : ar91xx_set_pll_ge0
;
542 pdata
->is_ar91xx
= 1;
550 switch (pdata
->phy_if_mode
) {
551 case PHY_INTERFACE_MODE_GMII
:
552 case PHY_INTERFACE_MODE_RGMII
:
553 if (!pdata
->has_gbit
) {
554 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
563 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
564 random_ether_addr(pdata
->mac_addr
);
566 "ar71xx: using random MAC address for eth%d\n",
567 ar71xx_eth_instance
);
570 if (pdata
->mii_bus_dev
== NULL
)
571 pdata
->mii_bus_dev
= &ar71xx_mdio_device
.dev
;
573 /* Reset the device */
574 ar71xx_device_stop(pdata
->reset_bit
);
577 ar71xx_device_start(pdata
->reset_bit
);
580 platform_device_register(pdev
);
581 ar71xx_eth_instance
++;
584 static struct resource ar71xx_spi_resources
[] = {
586 .start
= AR71XX_SPI_BASE
,
587 .end
= AR71XX_SPI_BASE
+ AR71XX_SPI_SIZE
- 1,
588 .flags
= IORESOURCE_MEM
,
592 static struct platform_device ar71xx_spi_device
= {
593 .name
= "ar71xx-spi",
595 .resource
= ar71xx_spi_resources
,
596 .num_resources
= ARRAY_SIZE(ar71xx_spi_resources
),
599 void __init
ar71xx_add_device_spi(struct ar71xx_spi_platform_data
*pdata
,
600 struct spi_board_info
const *info
,
603 spi_register_board_info(info
, n
);
604 ar71xx_spi_device
.dev
.platform_data
= pdata
;
605 platform_device_register(&ar71xx_spi_device
);
608 void __init
ar71xx_add_device_wdt(void)
610 platform_device_register_simple("ar71xx-wdt", -1, NULL
, 0);
613 void __init
ar71xx_set_mac_base(unsigned char *mac
)
615 memcpy(ar71xx_mac_base
, mac
, ETH_ALEN
);
618 void __init
ar71xx_parse_mac_addr(char *mac_str
)
623 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
624 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
627 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
628 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
631 ar71xx_set_mac_base(tmp
);
633 printk(KERN_DEBUG
"ar71xx: failed to parse mac address "
634 "\"%s\"\n", mac_str
);
637 static int __init
ar71xx_ethaddr_setup(char *str
)
639 ar71xx_parse_mac_addr(str
);
642 __setup("ethaddr=", ar71xx_ethaddr_setup
);
644 static int __init
ar71xx_kmac_setup(char *str
)
646 ar71xx_parse_mac_addr(str
);
649 __setup("kmac=", ar71xx_kmac_setup
);
651 void __init
ar71xx_init_mac(unsigned char *dst
, const unsigned char *src
,
656 if (!is_valid_ether_addr(src
)) {
657 memset(dst
, '\0', ETH_ALEN
);
661 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
667 dst
[3] = (t
>> 16) & 0xff;
668 dst
[4] = (t
>> 8) & 0xff;