2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
24 static void (* ar71xx_ip2_irq_handler
)(void) = spurious_interrupt
;
27 static void ar71xx_pci_irq_dispatch(void)
31 pending
= ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS
) &
32 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
34 if (pending
& PCI_INT_DEV0
)
35 do_IRQ(AR71XX_PCI_IRQ_DEV0
);
37 else if (pending
& PCI_INT_DEV1
)
38 do_IRQ(AR71XX_PCI_IRQ_DEV1
);
40 else if (pending
& PCI_INT_DEV2
)
41 do_IRQ(AR71XX_PCI_IRQ_DEV2
);
43 else if (pending
& PCI_INT_CORE
)
44 do_IRQ(AR71XX_PCI_IRQ_CORE
);
50 static void ar71xx_pci_irq_unmask(unsigned int irq
)
52 irq
-= AR71XX_PCI_IRQ_BASE
;
53 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
,
54 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
) | (1 << irq
));
57 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
60 static void ar71xx_pci_irq_mask(unsigned int irq
)
62 irq
-= AR71XX_PCI_IRQ_BASE
;
63 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
,
64 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
) & ~(1 << irq
));
67 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
70 static struct irq_chip ar71xx_pci_irq_chip
= {
71 .name
= "AR71XX PCI ",
72 .mask
= ar71xx_pci_irq_mask
,
73 .unmask
= ar71xx_pci_irq_unmask
,
74 .mask_ack
= ar71xx_pci_irq_mask
,
77 static struct irqaction ar71xx_pci_irqaction
= {
79 .name
= "cascade [AR71XX PCI]",
82 static void __init
ar71xx_pci_irq_init(void)
86 ar71xx_ip2_irq_handler
= ar71xx_pci_irq_dispatch
;
88 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
, 0);
89 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS
, 0);
91 for (i
= AR71XX_PCI_IRQ_BASE
;
92 i
< AR71XX_PCI_IRQ_BASE
+ AR71XX_PCI_IRQ_COUNT
; i
++) {
93 irq_desc
[i
].status
= IRQ_DISABLED
;
94 set_irq_chip_and_handler(i
, &ar71xx_pci_irq_chip
,
98 setup_irq(AR71XX_CPU_IRQ_PCI
, &ar71xx_pci_irqaction
);
101 static void ar724x_pci_irq_dispatch(void)
105 pending
= ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS
) &
106 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
);
108 if (pending
& AR724X_PCI_INT_DEV0
)
109 do_IRQ(AR71XX_PCI_IRQ_DEV0
);
112 spurious_interrupt();
115 static void ar724x_pci_irq_unmask(unsigned int irq
)
118 case AR71XX_PCI_IRQ_DEV0
:
119 irq
-= AR71XX_PCI_IRQ_BASE
;
120 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK
,
121 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
) |
122 AR724X_PCI_INT_DEV0
);
124 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
);
128 static void ar724x_pci_irq_mask(unsigned int irq
)
131 case AR71XX_PCI_IRQ_DEV0
:
132 irq
-= AR71XX_PCI_IRQ_BASE
;
133 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK
,
134 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
) &
135 ~AR724X_PCI_INT_DEV0
);
137 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK
);
139 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS
,
140 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS
) |
141 AR724X_PCI_INT_DEV0
);
143 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS
);
147 static struct irq_chip ar724x_pci_irq_chip
= {
148 .name
= "AR724X PCI ",
149 .mask
= ar724x_pci_irq_mask
,
150 .unmask
= ar724x_pci_irq_unmask
,
151 .mask_ack
= ar724x_pci_irq_mask
,
154 static struct irqaction ar724x_pci_irqaction
= {
155 .handler
= no_action
,
156 .name
= "cascade [AR724X PCI]",
159 static void __init
ar724x_pci_irq_init(void)
163 ar71xx_ip2_irq_handler
= ar724x_pci_irq_dispatch
;
165 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK
, 0);
166 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS
, 0);
168 for (i
= AR71XX_PCI_IRQ_BASE
;
169 i
< AR71XX_PCI_IRQ_BASE
+ AR71XX_PCI_IRQ_COUNT
; i
++) {
170 irq_desc
[i
].status
= IRQ_DISABLED
;
171 set_irq_chip_and_handler(i
, &ar724x_pci_irq_chip
,
175 setup_irq(AR71XX_CPU_IRQ_PCI
, &ar724x_pci_irqaction
);
178 static inline void ar71xx_pci_irq_init(void) {};
179 static inline void ar724x_pci_irq_init(void) {};
180 #endif /* CONFIG_PCI */
182 static void ar71xx_gpio_irq_dispatch(void)
186 pending
= ar71xx_gpio_rr(GPIO_REG_INT_PENDING
)
187 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
190 do_IRQ(AR71XX_GPIO_IRQ_BASE
+ fls(pending
) - 1);
192 spurious_interrupt();
195 static void ar71xx_gpio_irq_unmask(unsigned int irq
)
197 irq
-= AR71XX_GPIO_IRQ_BASE
;
198 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
,
199 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
) | (1 << irq
));
202 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
205 static void ar71xx_gpio_irq_mask(unsigned int irq
)
207 irq
-= AR71XX_GPIO_IRQ_BASE
;
208 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
,
209 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
) & ~(1 << irq
));
212 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
216 static int ar71xx_gpio_irq_set_type(unsigned int irq
, unsigned int flow_type
)
218 /* TODO: implement */
222 #define ar71xx_gpio_irq_set_type NULL
225 static struct irq_chip ar71xx_gpio_irq_chip
= {
226 .name
= "AR71XX GPIO",
227 .unmask
= ar71xx_gpio_irq_unmask
,
228 .mask
= ar71xx_gpio_irq_mask
,
229 .mask_ack
= ar71xx_gpio_irq_mask
,
230 .set_type
= ar71xx_gpio_irq_set_type
,
233 static struct irqaction ar71xx_gpio_irqaction
= {
234 .handler
= no_action
,
235 .name
= "cascade [AR71XX GPIO]",
238 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
239 #define GPIO_INT_ALL 0xffff
241 static void __init
ar71xx_gpio_irq_init(void)
245 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
, 0);
246 ar71xx_gpio_wr(GPIO_REG_INT_PENDING
, 0);
248 /* setup type of all GPIO interrupts to level sensitive */
249 ar71xx_gpio_wr(GPIO_REG_INT_TYPE
, GPIO_INT_ALL
);
251 /* setup polarity of all GPIO interrupts to active high */
252 ar71xx_gpio_wr(GPIO_REG_INT_POLARITY
, GPIO_INT_ALL
);
254 for (i
= AR71XX_GPIO_IRQ_BASE
;
255 i
< AR71XX_GPIO_IRQ_BASE
+ AR71XX_GPIO_IRQ_COUNT
; i
++) {
256 irq_desc
[i
].status
= GPIO_IRQ_INIT_STATUS
;
257 set_irq_chip_and_handler(i
, &ar71xx_gpio_irq_chip
,
261 setup_irq(AR71XX_MISC_IRQ_GPIO
, &ar71xx_gpio_irqaction
);
264 static void ar71xx_misc_irq_dispatch(void)
268 pending
= ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
)
269 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
271 if (pending
& MISC_INT_UART
)
272 do_IRQ(AR71XX_MISC_IRQ_UART
);
274 else if (pending
& MISC_INT_DMA
)
275 do_IRQ(AR71XX_MISC_IRQ_DMA
);
277 else if (pending
& MISC_INT_PERFC
)
278 do_IRQ(AR71XX_MISC_IRQ_PERFC
);
280 else if (pending
& MISC_INT_TIMER
)
281 do_IRQ(AR71XX_MISC_IRQ_TIMER
);
283 else if (pending
& MISC_INT_OHCI
)
284 do_IRQ(AR71XX_MISC_IRQ_OHCI
);
286 else if (pending
& MISC_INT_ERROR
)
287 do_IRQ(AR71XX_MISC_IRQ_ERROR
);
289 else if (pending
& MISC_INT_GPIO
)
290 ar71xx_gpio_irq_dispatch();
292 else if (pending
& MISC_INT_WDOG
)
293 do_IRQ(AR71XX_MISC_IRQ_WDOG
);
296 spurious_interrupt();
299 static void ar71xx_misc_irq_unmask(unsigned int irq
)
301 irq
-= AR71XX_MISC_IRQ_BASE
;
302 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
,
303 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
) | (1 << irq
));
306 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
309 static void ar71xx_misc_irq_mask(unsigned int irq
)
311 irq
-= AR71XX_MISC_IRQ_BASE
;
312 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
,
313 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
) & ~(1 << irq
));
316 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
319 static void ar724x_misc_irq_ack(unsigned int irq
)
321 irq
-= AR71XX_MISC_IRQ_BASE
;
322 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS
,
323 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
) & ~(1 << irq
));
326 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
);
329 static struct irq_chip ar71xx_misc_irq_chip
= {
330 .name
= "AR71XX MISC",
331 .unmask
= ar71xx_misc_irq_unmask
,
332 .mask
= ar71xx_misc_irq_mask
,
335 static struct irqaction ar71xx_misc_irqaction
= {
336 .handler
= no_action
,
337 .name
= "cascade [AR71XX MISC]",
340 static void __init
ar71xx_misc_irq_init(void)
344 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
, 0);
345 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS
, 0);
347 if (ar71xx_soc
== AR71XX_SOC_AR7240
)
348 ar71xx_misc_irq_chip
.ack
= ar724x_misc_irq_ack
;
350 ar71xx_misc_irq_chip
.mask_ack
= ar71xx_misc_irq_mask
;
352 for (i
= AR71XX_MISC_IRQ_BASE
;
353 i
< AR71XX_MISC_IRQ_BASE
+ AR71XX_MISC_IRQ_COUNT
; i
++) {
354 irq_desc
[i
].status
= IRQ_DISABLED
;
355 set_irq_chip_and_handler(i
, &ar71xx_misc_irq_chip
,
359 setup_irq(AR71XX_CPU_IRQ_MISC
, &ar71xx_misc_irqaction
);
362 static void ar913x_wmac_irq_dispatch(void)
364 do_IRQ(AR71XX_CPU_IRQ_WMAC
);
367 asmlinkage
void plat_irq_dispatch(void)
369 unsigned long pending
;
371 pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
373 if (pending
& STATUSF_IP7
)
374 do_IRQ(AR71XX_CPU_IRQ_TIMER
);
376 else if (pending
& STATUSF_IP2
)
377 ar71xx_ip2_irq_handler();
379 else if (pending
& STATUSF_IP4
)
380 do_IRQ(AR71XX_CPU_IRQ_GE0
);
382 else if (pending
& STATUSF_IP5
)
383 do_IRQ(AR71XX_CPU_IRQ_GE1
);
385 else if (pending
& STATUSF_IP3
)
386 do_IRQ(AR71XX_CPU_IRQ_USB
);
388 else if (pending
& STATUSF_IP6
)
389 ar71xx_misc_irq_dispatch();
392 spurious_interrupt();
395 void __init
arch_init_irq(void)
399 ar71xx_misc_irq_init();
401 switch (ar71xx_soc
) {
402 case AR71XX_SOC_AR7130
:
403 case AR71XX_SOC_AR7141
:
404 case AR71XX_SOC_AR7161
:
405 ar71xx_pci_irq_init();
407 case AR71XX_SOC_AR7240
:
408 ar724x_pci_irq_init();
410 case AR71XX_SOC_AR9130
:
411 case AR71XX_SOC_AR9132
:
412 ar71xx_ip2_irq_handler
= ar913x_wmac_irq_dispatch
;
418 ar71xx_gpio_irq_init();