2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/etherdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/serial_8250.h>
21 #include <linux/ath9k_platform.h>
23 #include <asm/mach-ar71xx/ar71xx.h>
24 #include <asm/mach-ar71xx/platform.h>
26 static u8 ar71xx_mac_base
[ETH_ALEN
] __initdata
;
29 * OHCI (USB full speed host controller)
31 static struct resource ar71xx_ohci_resources
[] = {
33 .start
= AR71XX_OHCI_BASE
,
34 .end
= AR71XX_OHCI_BASE
+ AR71XX_OHCI_SIZE
- 1,
35 .flags
= IORESOURCE_MEM
,
38 .start
= AR71XX_MISC_IRQ_OHCI
,
39 .end
= AR71XX_MISC_IRQ_OHCI
,
40 .flags
= IORESOURCE_IRQ
,
44 static u64 ar71xx_ohci_dmamask
= DMA_BIT_MASK(32);
45 static struct platform_device ar71xx_ohci_device
= {
46 .name
= "ar71xx-ohci",
48 .resource
= ar71xx_ohci_resources
,
49 .num_resources
= ARRAY_SIZE(ar71xx_ohci_resources
),
51 .dma_mask
= &ar71xx_ohci_dmamask
,
52 .coherent_dma_mask
= DMA_BIT_MASK(32),
57 * EHCI (USB full speed host controller)
59 static struct resource ar71xx_ehci_resources
[] = {
61 .start
= AR71XX_EHCI_BASE
,
62 .end
= AR71XX_EHCI_BASE
+ AR71XX_EHCI_SIZE
- 1,
63 .flags
= IORESOURCE_MEM
,
66 .start
= AR71XX_CPU_IRQ_USB
,
67 .end
= AR71XX_CPU_IRQ_USB
,
68 .flags
= IORESOURCE_IRQ
,
73 static u64 ar71xx_ehci_dmamask
= DMA_BIT_MASK(32);
74 static struct ar71xx_ehci_platform_data ar71xx_ehci_data
;
76 static struct platform_device ar71xx_ehci_device
= {
77 .name
= "ar71xx-ehci",
79 .resource
= ar71xx_ehci_resources
,
80 .num_resources
= ARRAY_SIZE(ar71xx_ehci_resources
),
82 .dma_mask
= &ar71xx_ehci_dmamask
,
83 .coherent_dma_mask
= DMA_BIT_MASK(32),
84 .platform_data
= &ar71xx_ehci_data
,
88 #define AR71XX_USB_RESET_MASK \
89 (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \
90 | RESET_MODULE_USB_OHCI_DLL)
92 static void ar71xx_usb_setup(void)
94 ar71xx_device_stop(AR71XX_USB_RESET_MASK
);
96 ar71xx_device_start(AR71XX_USB_RESET_MASK
);
98 /* Turning on the Buff and Desc swap bits */
99 ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG
, 0xf0000);
101 /* WAR for HW bug. Here it adjusts the duration between two SOFS */
102 ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ
, 0x20c00);
107 static void ar91xx_usb_setup(void)
109 ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE
);
112 ar71xx_device_start(RESET_MODULE_USB_HOST
);
115 ar71xx_device_start(RESET_MODULE_USB_PHY
);
119 void __init
ar71xx_add_device_usb(void)
121 switch (ar71xx_soc
) {
122 case AR71XX_SOC_AR7130
:
123 case AR71XX_SOC_AR7141
:
124 case AR71XX_SOC_AR7161
:
126 platform_device_register(&ar71xx_ohci_device
);
127 platform_device_register(&ar71xx_ehci_device
);
130 case AR71XX_SOC_AR9130
:
131 case AR71XX_SOC_AR9132
:
133 ar71xx_ehci_data
.is_ar91xx
= 1;
134 platform_device_register(&ar71xx_ehci_device
);
142 #ifndef CONFIG_AR71XX_EARLY_SERIAL
143 static struct resource ar71xx_uart_resources
[] = {
145 .start
= AR71XX_UART_BASE
,
146 .end
= AR71XX_UART_BASE
+ AR71XX_UART_SIZE
- 1,
147 .flags
= IORESOURCE_MEM
,
151 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
152 static struct plat_serial8250_port ar71xx_uart_data
[] = {
154 .mapbase
= AR71XX_UART_BASE
,
155 .irq
= AR71XX_MISC_IRQ_UART
,
156 .flags
= AR71XX_UART_FLAGS
,
157 .iotype
= UPIO_MEM32
,
160 /* terminating entry */
164 static struct platform_device ar71xx_uart_device
= {
165 .name
= "serial8250",
166 .id
= PLAT8250_DEV_PLATFORM
,
167 .resource
= ar71xx_uart_resources
,
168 .num_resources
= ARRAY_SIZE(ar71xx_uart_resources
),
170 .platform_data
= ar71xx_uart_data
174 void __init
ar71xx_add_device_uart(void)
176 ar71xx_uart_data
[0].uartclk
= ar71xx_ahb_freq
;
177 platform_device_register(&ar71xx_uart_device
);
179 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
181 static struct resource ar71xx_mdio_resources
[] = {
184 .flags
= IORESOURCE_MEM
,
185 .start
= AR71XX_GE0_BASE
+ 0x20,
186 .end
= AR71XX_GE0_BASE
+ 0x38 - 1,
190 static struct ag71xx_mdio_platform_data ar71xx_mdio_data
= {
191 .phy_mask
= 0xffffffff,
194 static struct platform_device ar71xx_mdio_device
= {
195 .name
= "ag71xx-mdio",
197 .resource
= ar71xx_mdio_resources
,
198 .num_resources
= ARRAY_SIZE(ar71xx_mdio_resources
),
200 .platform_data
= &ar71xx_mdio_data
,
204 void __init
ar71xx_add_device_mdio(u32 phy_mask
)
206 ar71xx_mdio_data
.phy_mask
= phy_mask
;
207 platform_device_register(&ar71xx_mdio_device
);
210 static void ar71xx_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
215 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
217 t
= __raw_readl(base
+ cfg_reg
);
220 __raw_writel(t
, base
+ cfg_reg
);
223 __raw_writel(pll_val
, base
+ pll_reg
);
226 __raw_writel(t
, base
+ cfg_reg
);
230 __raw_writel(t
, base
+ cfg_reg
);
233 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
234 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
239 static void ar71xx_set_pll_ge0(u32 val
)
241 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
242 val
, AR71XX_ETH0_PLL_SHIFT
);
245 static void ar71xx_set_pll_ge1(u32 val
)
247 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
248 val
, AR71XX_ETH1_PLL_SHIFT
);
251 static void ar91xx_set_pll_ge0(u32 val
)
253 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH0_INT_CLOCK
,
254 val
, AR91XX_ETH0_PLL_SHIFT
);
257 static void ar91xx_set_pll_ge1(u32 val
)
259 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH1_INT_CLOCK
,
260 val
, AR91XX_ETH1_PLL_SHIFT
);
263 static void ar71xx_ddr_flush_ge0(void)
265 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0
);
268 static void ar71xx_ddr_flush_ge1(void)
270 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1
);
273 static void ar91xx_ddr_flush_ge0(void)
275 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0
);
278 static void ar91xx_ddr_flush_ge1(void)
280 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1
);
283 static struct resource ar71xx_eth0_resources
[] = {
286 .flags
= IORESOURCE_MEM
,
287 .start
= AR71XX_GE0_BASE
,
288 .end
= AR71XX_GE0_BASE
+ 0x20 - 1,
291 .flags
= IORESOURCE_MEM
,
292 .start
= AR71XX_GE0_BASE
+ 0x38,
293 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
296 .flags
= IORESOURCE_MEM
,
297 .start
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
,
298 .end
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
+ 3,
301 .flags
= IORESOURCE_IRQ
,
302 .start
= AR71XX_CPU_IRQ_GE0
,
303 .end
= AR71XX_CPU_IRQ_GE0
,
307 struct ag71xx_platform_data ar71xx_eth0_data
= {
308 .reset_bit
= RESET_MODULE_GE0_MAC
,
311 static struct platform_device ar71xx_eth0_device
= {
314 .resource
= ar71xx_eth0_resources
,
315 .num_resources
= ARRAY_SIZE(ar71xx_eth0_resources
),
317 .platform_data
= &ar71xx_eth0_data
,
321 static struct resource ar71xx_eth1_resources
[] = {
324 .flags
= IORESOURCE_MEM
,
325 .start
= AR71XX_GE1_BASE
,
326 .end
= AR71XX_GE1_BASE
+ 0x20 - 1,
329 .flags
= IORESOURCE_MEM
,
330 .start
= AR71XX_GE1_BASE
+ 0x38,
331 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
334 .flags
= IORESOURCE_MEM
,
335 .start
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
,
336 .end
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
+ 3,
339 .flags
= IORESOURCE_IRQ
,
340 .start
= AR71XX_CPU_IRQ_GE1
,
341 .end
= AR71XX_CPU_IRQ_GE1
,
345 struct ag71xx_platform_data ar71xx_eth1_data
= {
346 .reset_bit
= RESET_MODULE_GE1_MAC
,
349 static struct platform_device ar71xx_eth1_device
= {
352 .resource
= ar71xx_eth1_resources
,
353 .num_resources
= ARRAY_SIZE(ar71xx_eth1_resources
),
355 .platform_data
= &ar71xx_eth1_data
,
359 static int ar71xx_eth_instance __initdata
;
360 void __init
ar71xx_add_device_eth(unsigned int id
)
362 struct platform_device
*pdev
;
363 struct ag71xx_platform_data
*pdata
;
367 switch (ar71xx_eth0_data
.phy_if_mode
) {
368 case PHY_INTERFACE_MODE_MII
:
369 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_MII
;
371 case PHY_INTERFACE_MODE_GMII
:
372 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_GMII
;
374 case PHY_INTERFACE_MODE_RGMII
:
375 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RGMII
;
377 case PHY_INTERFACE_MODE_RMII
:
378 ar71xx_eth0_data
.mii_if
= MII0_CTRL_IF_RMII
;
381 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
385 pdev
= &ar71xx_eth0_device
;
388 switch (ar71xx_eth1_data
.phy_if_mode
) {
389 case PHY_INTERFACE_MODE_RMII
:
390 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RMII
;
392 case PHY_INTERFACE_MODE_RGMII
:
393 ar71xx_eth1_data
.mii_if
= MII1_CTRL_IF_RGMII
;
396 printk(KERN_ERR
"ar71xx: invalid PHY interface mode "
400 pdev
= &ar71xx_eth1_device
;
403 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
407 pdata
= pdev
->dev
.platform_data
;
409 switch (ar71xx_soc
) {
410 case AR71XX_SOC_AR7130
:
411 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
412 : ar71xx_ddr_flush_ge0
;
413 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
414 : ar71xx_set_pll_ge0
;
417 case AR71XX_SOC_AR7141
:
418 case AR71XX_SOC_AR7161
:
419 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
420 : ar71xx_ddr_flush_ge0
;
421 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
422 : ar71xx_set_pll_ge0
;
426 case AR71XX_SOC_AR9130
:
427 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
428 : ar91xx_ddr_flush_ge0
;
429 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
430 : ar91xx_set_pll_ge0
;
431 pdata
->is_ar91xx
= 1;
434 case AR71XX_SOC_AR9132
:
435 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
436 : ar91xx_ddr_flush_ge0
;
437 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
438 : ar91xx_set_pll_ge0
;
439 pdata
->is_ar91xx
= 1;
447 switch (pdata
->phy_if_mode
) {
448 case PHY_INTERFACE_MODE_GMII
:
449 case PHY_INTERFACE_MODE_RGMII
:
450 if (!pdata
->has_gbit
) {
451 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
460 if (is_valid_ether_addr(ar71xx_mac_base
)) {
461 memcpy(pdata
->mac_addr
, ar71xx_mac_base
, ETH_ALEN
);
462 pdata
->mac_addr
[5] += ar71xx_eth_instance
;
464 random_ether_addr(pdata
->mac_addr
);
466 "ar71xx: using random MAC address for eth%d\n",
467 ar71xx_eth_instance
);
470 platform_device_register(pdev
);
471 ar71xx_eth_instance
++;
474 static struct resource ar71xx_spi_resources
[] = {
476 .start
= AR71XX_SPI_BASE
,
477 .end
= AR71XX_SPI_BASE
+ AR71XX_SPI_SIZE
- 1,
478 .flags
= IORESOURCE_MEM
,
482 static struct platform_device ar71xx_spi_device
= {
483 .name
= "ar71xx-spi",
485 .resource
= ar71xx_spi_resources
,
486 .num_resources
= ARRAY_SIZE(ar71xx_spi_resources
),
489 void __init
ar71xx_add_device_spi(struct ar71xx_spi_platform_data
*pdata
,
490 struct spi_board_info
const *info
,
493 spi_register_board_info(info
, n
);
494 ar71xx_spi_device
.dev
.platform_data
= pdata
;
495 platform_device_register(&ar71xx_spi_device
);
498 void __init
ar71xx_add_device_leds_gpio(int id
, unsigned num_leds
,
499 struct gpio_led
*leds
)
501 struct platform_device
*pdev
;
502 struct gpio_led_platform_data pdata
;
506 p
= kmalloc(num_leds
* sizeof(*p
), GFP_KERNEL
);
510 memcpy(p
, leds
, num_leds
* sizeof(*p
));
512 pdev
= platform_device_alloc("leds-gpio", id
);
516 memset(&pdata
, 0, sizeof(pdata
));
517 pdata
.num_leds
= num_leds
;
520 err
= platform_device_add_data(pdev
, &pdata
, sizeof(pdata
));
524 err
= platform_device_add(pdev
);
531 platform_device_put(pdev
);
537 void __init
ar71xx_add_device_gpio_buttons(int id
,
538 unsigned poll_interval
,
540 struct gpio_button
*buttons
)
542 struct platform_device
*pdev
;
543 struct gpio_buttons_platform_data pdata
;
544 struct gpio_button
*p
;
547 p
= kmalloc(nbuttons
* sizeof(*p
), GFP_KERNEL
);
551 memcpy(p
, buttons
, nbuttons
* sizeof(*p
));
553 pdev
= platform_device_alloc("gpio-buttons", id
);
555 goto err_free_buttons
;
557 memset(&pdata
, 0, sizeof(pdata
));
558 pdata
.poll_interval
= poll_interval
;
559 pdata
.nbuttons
= nbuttons
;
562 err
= platform_device_add_data(pdev
, &pdata
, sizeof(pdata
));
567 err
= platform_device_add(pdev
);
574 platform_device_put(pdev
);
580 void __init
ar71xx_add_device_wdt(void)
582 platform_device_register_simple("ar71xx-wdt", -1, NULL
, 0);
585 void __init
ar71xx_set_mac_base(unsigned char *mac
)
587 memcpy(ar71xx_mac_base
, mac
, ETH_ALEN
);
590 void __init
ar71xx_parse_mac_addr(char *mac_str
)
595 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
596 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
599 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
600 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
603 ar71xx_set_mac_base(tmp
);
605 printk(KERN_DEBUG
"ar71xx: failed to parse mac address "
606 "\"%s\"\n", mac_str
);
609 static struct resource ar91xx_wmac_resources
[] = {
611 .start
= AR91XX_WMAC_BASE
,
612 .end
= AR91XX_WMAC_BASE
+ AR91XX_WMAC_SIZE
- 1,
613 .flags
= IORESOURCE_MEM
,
615 .start
= AR71XX_CPU_IRQ_WMAC
,
616 .end
= AR71XX_CPU_IRQ_WMAC
,
617 .flags
= IORESOURCE_IRQ
,
621 static struct ath9k_platform_data ar91xx_wmac_data
;
623 static struct platform_device ar91xx_wmac_device
= {
626 .resource
= ar91xx_wmac_resources
,
627 .num_resources
= ARRAY_SIZE(ar91xx_wmac_resources
),
629 .platform_data
= &ar91xx_wmac_data
,
633 void __init
ar91xx_add_device_wmac(void)
635 u8
*ee
= (u8
*) KSEG1ADDR(0x1fff1000);
637 memcpy(ar91xx_wmac_data
.eeprom_data
, ee
,
638 sizeof(ar91xx_wmac_data
.eeprom_data
));
640 ar71xx_device_stop(RESET_MODULE_AMBA2WMAC
);
643 ar71xx_device_start(RESET_MODULE_AMBA2WMAC
);
646 platform_device_register(&ar91xx_wmac_device
);