2 * Atheros AR71xx SoC specific setup
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/bootinfo.h>
21 #include <asm/time.h> /* for mips_hpt_frequency */
22 #include <asm/reboot.h> /* for _machine_{restart,halt} */
23 #include <asm/mips_machine.h>
25 #include <asm/mach-ar71xx/ar71xx.h>
30 #define AR71XX_SYS_TYPE_LEN 64
33 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq
);
36 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq
);
39 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq
);
42 EXPORT_SYMBOL_GPL(ar71xx_ref_freq
);
44 enum ar71xx_soc_type ar71xx_soc
;
45 EXPORT_SYMBOL_GPL(ar71xx_soc
);
48 EXPORT_SYMBOL_GPL(ar71xx_soc_rev
);
50 static char ar71xx_sys_type
[AR71XX_SYS_TYPE_LEN
];
52 static void ar71xx_restart(char *command
)
54 ar71xx_device_stop(RESET_MODULE_FULL_CHIP
);
60 static void ar71xx_halt(void)
66 static void __init
ar71xx_detect_mem_size(void)
70 for (size
= AR71XX_MEM_SIZE_MIN
; size
< AR71XX_MEM_SIZE_MAX
;
72 if (!memcmp(ar71xx_detect_mem_size
,
73 ar71xx_detect_mem_size
+ size
, 1024))
77 add_memory_region(0, size
, BOOT_MEM_RAM
);
80 static void __init
ar71xx_detect_sys_type(void)
88 id
= ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID
);
89 major
= id
& REV_ID_MAJOR_MASK
;
92 case REV_ID_MAJOR_AR71XX
:
93 minor
= id
& AR71XX_REV_ID_MINOR_MASK
;
94 rev
= id
>> AR71XX_REV_ID_REVISION_SHIFT
;
95 rev
&= AR71XX_REV_ID_REVISION_MASK
;
97 case AR71XX_REV_ID_MINOR_AR7130
:
98 ar71xx_soc
= AR71XX_SOC_AR7130
;
102 case AR71XX_REV_ID_MINOR_AR7141
:
103 ar71xx_soc
= AR71XX_SOC_AR7141
;
107 case AR71XX_REV_ID_MINOR_AR7161
:
108 ar71xx_soc
= AR71XX_SOC_AR7161
;
114 case REV_ID_MAJOR_AR7240
:
115 ar71xx_soc
= AR71XX_SOC_AR7240
;
117 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
120 case REV_ID_MAJOR_AR7241
:
121 ar71xx_soc
= AR71XX_SOC_AR7241
;
123 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
126 case REV_ID_MAJOR_AR7242
:
127 ar71xx_soc
= AR71XX_SOC_AR7242
;
129 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
132 case REV_ID_MAJOR_AR913X
:
133 minor
= id
& AR91XX_REV_ID_MINOR_MASK
;
134 rev
= id
>> AR91XX_REV_ID_REVISION_SHIFT
;
135 rev
&= AR91XX_REV_ID_REVISION_MASK
;
137 case AR91XX_REV_ID_MINOR_AR9130
:
138 ar71xx_soc
= AR71XX_SOC_AR9130
;
142 case AR91XX_REV_ID_MINOR_AR9132
:
143 ar71xx_soc
= AR71XX_SOC_AR9132
;
149 case REV_ID_MAJOR_AR9330
:
150 ar71xx_soc
= AR71XX_SOC_AR9330
;
152 rev
= id
& AR933X_REV_ID_REVISION_MASK
;
155 case REV_ID_MAJOR_AR9331
:
156 ar71xx_soc
= AR71XX_SOC_AR9331
;
158 rev
= id
& AR933X_REV_ID_REVISION_MASK
;
161 case REV_ID_MAJOR_AR9342
:
162 ar71xx_soc
= AR71XX_SOC_AR9342
;
164 rev
= id
& AR934X_REV_ID_REVISION_MASK
;
167 case REV_ID_MAJOR_AR9344
:
168 ar71xx_soc
= AR71XX_SOC_AR9344
;
170 rev
= id
& AR934X_REV_ID_REVISION_MASK
;
174 panic("ar71xx: unknown chip id:0x%08x\n", id
);
177 ar71xx_soc_rev
= rev
;
179 sprintf(ar71xx_sys_type
, "Atheros AR%s rev %u", chip
, rev
);
180 pr_info("SoC: %s\n", ar71xx_sys_type
);
183 static void __init
ar934x_detect_sys_frequency(void)
185 u32 pll
, out_div
, ref_div
, nint
, frac
, clk_ctrl
, postdiv
;
186 u32 cpu_pll
, ddr_pll
;
189 bootstrap
= ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP
);
190 if (bootstrap
& AR934X_BOOTSTRAP_REF_CLK_40
)
191 ar71xx_ref_freq
= 40 * 1000 * 1000;
193 ar71xx_ref_freq
= 25 * 1000 * 1000;
195 pll
= ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG
);
196 out_div
= AR934X_CPU_PLL_CFG_OUTDIV_GET(pll
);
197 ref_div
= AR934X_CPU_PLL_CFG_REFDIV_GET(pll
);
198 nint
= AR934X_CPU_PLL_CFG_NINT_GET(pll
);
199 frac
= AR934X_CPU_PLL_CFG_NFRAC_GET(pll
);
201 cpu_pll
= nint
* ar71xx_ref_freq
/ ref_div
;
202 cpu_pll
+= frac
* ar71xx_ref_freq
/ (ref_div
* (2 << 6));
203 cpu_pll
/= (1 << out_div
);
205 pll
= ar71xx_pll_rr(AR934X_PLL_REG_DDR_CONFIG
);
206 out_div
= AR934X_DDR_PLL_CFG_OUTDIV_GET(pll
);
207 ref_div
= AR934X_DDR_PLL_CFG_REFDIV_GET(pll
);
208 nint
= AR934X_DDR_PLL_CFG_NINT_GET(pll
);
209 frac
= AR934X_DDR_PLL_CFG_NFRAC_GET(pll
);
211 ddr_pll
= nint
* ar71xx_ref_freq
/ ref_div
;
212 ddr_pll
+= frac
* ar71xx_ref_freq
/ (ref_div
* (2 << 10));
213 ddr_pll
/= (1 << out_div
);
215 clk_ctrl
= ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK
);
217 if (clk_ctrl
& AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS
) {
218 ar71xx_cpu_freq
= ar71xx_ref_freq
;
220 postdiv
= AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl
);
222 if (clk_ctrl
& AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL
)
223 ar71xx_cpu_freq
= cpu_pll
/ (postdiv
+ 1);
225 ar71xx_cpu_freq
= ddr_pll
/ (postdiv
+ 1);
228 if (clk_ctrl
& AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS
) {
229 ar71xx_ddr_freq
= ar71xx_ref_freq
;
231 postdiv
= AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl
);
233 if (clk_ctrl
& AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL
)
234 ar71xx_ddr_freq
= ddr_pll
/ (postdiv
+ 1);
236 ar71xx_ddr_freq
= cpu_pll
/ (postdiv
+ 1);
239 if (clk_ctrl
& AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS
) {
240 ar71xx_ahb_freq
= ar71xx_ref_freq
;
242 postdiv
= AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl
);
244 if (clk_ctrl
& AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL
)
245 ar71xx_ahb_freq
= ddr_pll
/ (postdiv
+ 1);
247 ar71xx_ahb_freq
= cpu_pll
/ (postdiv
+ 1);
251 static void __init
ar91xx_detect_sys_frequency(void)
257 ar71xx_ref_freq
= 5 * 1000 * 1000;
259 pll
= ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG
);
261 div
= ((pll
>> AR91XX_PLL_DIV_SHIFT
) & AR91XX_PLL_DIV_MASK
);
262 freq
= div
* ar71xx_ref_freq
;
264 ar71xx_cpu_freq
= freq
;
266 div
= ((pll
>> AR91XX_DDR_DIV_SHIFT
) & AR91XX_DDR_DIV_MASK
) + 1;
267 ar71xx_ddr_freq
= freq
/ div
;
269 div
= (((pll
>> AR91XX_AHB_DIV_SHIFT
) & AR91XX_AHB_DIV_MASK
) + 1) * 2;
270 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
273 static void __init
ar71xx_detect_sys_frequency(void)
279 ar71xx_ref_freq
= 40 * 1000 * 1000;
281 pll
= ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG
);
283 div
= ((pll
>> AR71XX_PLL_DIV_SHIFT
) & AR71XX_PLL_DIV_MASK
) + 1;
284 freq
= div
* ar71xx_ref_freq
;
286 div
= ((pll
>> AR71XX_CPU_DIV_SHIFT
) & AR71XX_CPU_DIV_MASK
) + 1;
287 ar71xx_cpu_freq
= freq
/ div
;
289 div
= ((pll
>> AR71XX_DDR_DIV_SHIFT
) & AR71XX_DDR_DIV_MASK
) + 1;
290 ar71xx_ddr_freq
= freq
/ div
;
292 div
= (((pll
>> AR71XX_AHB_DIV_SHIFT
) & AR71XX_AHB_DIV_MASK
) + 1) * 2;
293 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
296 static void __init
ar724x_detect_sys_frequency(void)
302 ar71xx_ref_freq
= 5 * 1000 * 1000;
304 pll
= ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG
);
306 div
= ((pll
>> AR724X_PLL_DIV_SHIFT
) & AR724X_PLL_DIV_MASK
);
307 freq
= div
* ar71xx_ref_freq
;
309 div
= ((pll
>> AR724X_PLL_REF_DIV_SHIFT
) & AR724X_PLL_REF_DIV_MASK
);
312 ar71xx_cpu_freq
= freq
;
314 div
= ((pll
>> AR724X_DDR_DIV_SHIFT
) & AR724X_DDR_DIV_MASK
) + 1;
315 ar71xx_ddr_freq
= freq
/ div
;
317 div
= (((pll
>> AR724X_AHB_DIV_SHIFT
) & AR724X_AHB_DIV_MASK
) + 1) * 2;
318 ar71xx_ahb_freq
= ar71xx_cpu_freq
/ div
;
321 static void __init
ar933x_detect_sys_frequency(void)
328 t
= ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP
);
329 if (t
& AR933X_BOOTSTRAP_REF_CLK_40
)
330 ar71xx_ref_freq
= (40 * 1000 * 1000);
332 ar71xx_ref_freq
= (25 * 1000 * 1000);
334 clock_ctrl
= ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG
);
335 if (clock_ctrl
& AR933X_PLL_CLOCK_CTRL_BYPASS
) {
336 ar71xx_cpu_freq
= ar71xx_ref_freq
;
337 ar71xx_ahb_freq
= ar71xx_ref_freq
;
338 ar71xx_ddr_freq
= ar71xx_ref_freq
;
340 cpu_config
= ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG
);
342 t
= (cpu_config
>> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT
) &
343 AR933X_PLL_CPU_CONFIG_REFDIV_MASK
;
344 freq
= ar71xx_ref_freq
/ t
;
346 t
= (cpu_config
>> AR933X_PLL_CPU_CONFIG_NINT_SHIFT
) &
347 AR933X_PLL_CPU_CONFIG_NINT_MASK
;
350 t
= (cpu_config
>> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT
) &
351 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK
;
357 t
= ((clock_ctrl
>> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT
) &
358 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK
) + 1;
359 ar71xx_cpu_freq
= freq
/ t
;
361 t
= ((clock_ctrl
>> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT
) &
362 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK
) + 1;
363 ar71xx_ddr_freq
= freq
/ t
;
365 t
= ((clock_ctrl
>> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT
) &
366 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK
) + 1;
367 ar71xx_ahb_freq
= freq
/ t
;
371 static void __init
detect_sys_frequency(void)
373 switch (ar71xx_soc
) {
374 case AR71XX_SOC_AR7130
:
375 case AR71XX_SOC_AR7141
:
376 case AR71XX_SOC_AR7161
:
377 ar71xx_detect_sys_frequency();
380 case AR71XX_SOC_AR7240
:
381 case AR71XX_SOC_AR7241
:
382 case AR71XX_SOC_AR7242
:
383 ar724x_detect_sys_frequency();
386 case AR71XX_SOC_AR9130
:
387 case AR71XX_SOC_AR9132
:
388 ar91xx_detect_sys_frequency();
391 case AR71XX_SOC_AR9330
:
392 case AR71XX_SOC_AR9331
:
393 ar933x_detect_sys_frequency();
396 case AR71XX_SOC_AR9341
:
397 case AR71XX_SOC_AR9342
:
398 case AR71XX_SOC_AR9344
:
399 ar934x_detect_sys_frequency();
406 const char *get_system_type(void)
408 return ar71xx_sys_type
;
411 unsigned int __cpuinit
get_c0_compare_irq(void)
413 return CP0_LEGACY_COMPARE_IRQ
;
416 void __init
plat_mem_setup(void)
418 set_io_port_base(KSEG1
);
420 ar71xx_ddr_base
= ioremap_nocache(AR71XX_DDR_CTRL_BASE
,
421 AR71XX_DDR_CTRL_SIZE
);
423 ar71xx_pll_base
= ioremap_nocache(AR71XX_PLL_BASE
,
426 ar71xx_reset_base
= ioremap_nocache(AR71XX_RESET_BASE
,
429 ar71xx_gpio_base
= ioremap_nocache(AR71XX_GPIO_BASE
, AR71XX_GPIO_SIZE
);
431 ar71xx_usb_ctrl_base
= ioremap_nocache(AR71XX_USB_CTRL_BASE
,
432 AR71XX_USB_CTRL_SIZE
);
434 ar71xx_detect_mem_size();
435 ar71xx_detect_sys_type();
436 detect_sys_frequency();
438 pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, "
440 ar71xx_cpu_freq
/ 1000000, (ar71xx_cpu_freq
/ 1000) % 1000,
441 ar71xx_ddr_freq
/ 1000000, (ar71xx_ddr_freq
/ 1000) % 1000,
442 ar71xx_ahb_freq
/ 1000000, (ar71xx_ahb_freq
/ 1000) % 1000,
443 ar71xx_ref_freq
/ 1000000, (ar71xx_ref_freq
/ 1000) % 1000);
445 _machine_restart
= ar71xx_restart
;
446 _machine_halt
= ar71xx_halt
;
447 pm_power_off
= ar71xx_halt
;
450 void __init
plat_time_init(void)
452 mips_hpt_frequency
= ar71xx_cpu_freq
/ 2;
455 __setup("board=", mips_machtype_setup
);
457 static int __init
ar71xx_machine_setup(void)
461 ar71xx_add_device_uart();
462 ar71xx_add_device_wdt();
464 mips_machine_setup();
468 arch_initcall(ar71xx_machine_setup
);
470 static void __init
ar71xx_generic_init(void)
475 MIPS_MACHINE(AR71XX_MACH_GENERIC
, "Generic", "Generic AR71xx board",
476 ar71xx_generic_init
);